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electrical specifications subject to change LT8705 1 8705p for more information www.linear.com/8705 typical application features description 80v v in and v out synchronous 4-switch buck- boost dc/dc controller the lt ? 8705 is a high performance buck-boost switch - ing regulator controller that operates from input voltages above, below or equal to the output voltage. the part has integrated input current, input voltage, output current and output voltage feedback loops. with a wide 2.8v to 80v input and 1.3v to 80v output range, the LT8705 is compatible with most solar, automotive, telecom and battery-powered systems. the operating mode of the controller is determined through the mode pin. the mode pin can select among discontinuous mode, forced continuous mode and burst mode ? operation. the LT8705 also features programmable uvlo and switching currents, along with input and output current monitoring with programmable maximum levels. applications l , lt, ltc, ltm, linear technology, burst mode, module and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. n single inductor allows v in above, below, or equal to regulated v out n v in range 2.8v (need extv cc > 6.4v) to 80v n v out range: 1.3v to 80v n quad n-channel mosfet gate drivers n synchronous rectification: up to 98% efficiency n input and output current monitor pins n synchronizable fixed frequency: 100khz to 400khz n integrated input current, input voltage, output current and output voltage feedback loops n clock output usable to monitor die temperature n available in 38-lead (5mm 7mm) qfn and tssop packages with the tssop modified for improved high voltage operation n high voltage buck-boost converters n input or output current limited converters telecom voltage stabilizer 8705 ta01 cspout csnout extv cc fbout intv cc gatev cc srvo_fbin srvo_fbout srvo_iin srvo_iout imon_in imon_out sync clkout v c 56.2k 202khz csnin tg1 boost1 0.22f 0.22f to diode to diode m2 m1 2 22h 4.7f 4 m4 m3 2 1nf 1nf sw1 bg1 csp csn LT8705 gnd bg2 sw2 boost2 v out 48v 5a v in 36v to 80v tg2 cspin v in shdn swen ldo33 mode fbin rt ss 3.3nf 220pf 215k 71.5k 20k 1f 1f 4.7f 10k 392k 220f 2 4.7f 6 4 4.7f to boost1 4.7f 2 2 2 2 10m + 220f 2 + to boost2 100k 10 10 v in (v) 30 efficiency (%) power loss (w) 90 95 70 8705 ta01b 85 80 0 40 50 60 80 v out = 48v i load = 2a 100 6 5 4 3 2 1 efficiency and power loss http:///
LT8705 2 8705p for more information www.linear.com/8705 pin configuration absolute maximum ratings v csp -v csn , v cspin -v csnin , v cspout -v csnout ...................................... C0.3v to 0.3v ss, clkout, csp, csn voltage ................... C0.3v to 3v v c voltage (note 2) ................................... C0.3v to 2.2v rt, ldo33, fbout voltage .......................... C0.3v to 5v imon_in, imon_out voltage ..................... C0.3v to 5v sync voltage ............................................ C0.3v to 5.5v intv cc , gatev cc voltage ............................ C0.3v to 7v v boost1 -v sw1 , v boost2 -v sw2 ..................... C0.3v to 7v swen, mode voltage .................................. C0.3v to 7v srvo_fbin, srvo_fbout voltage ........... C0.3v to 30v srvo_iin, srvo_iout voltage ................. C0.3v to 30v (note 1) fbin, shdn voltage ................................... C0.3v to 30v csnin, cspin, cspout, csnout voltage .. C0.3v to 80v v in , extv cc voltage .................................. C0.3v to 80v sw1, sw2 voltage ...................................... 81v (note 7) boost1, boost2 voltage ......................... C0.3v to 87v bg1, bg2, tg1, tg2 ........................................... (note 6) operating junction temperature range LT8705e (notes 1, 3) ......................... C40c to 125c LT8705i (notes 1, 3) .......................... C40c to 125c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) fe package ....................................................... 300c 13 14 15 16 top view 39 gnd uhf package 38-lead (5mm 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 shdn csn csp ldo33 fbin fbout imon_out v c ss clkout sync rt cspout csnout extv cc srvo_fbout srvo_iout srvo_iin srvo_fbin nc boost1 tg1 sw1 nc imon_in mode swen intv cc v in cspin csnin gnd bg1 gatev cc bg2 boost2 tg2 sw2 23 22 21 20 9 10 11 12 t jmax = 125c, ja = 34c/w exposed pad (pin 39) is gnd, must be soldered to pcb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 top view fe package variation: fe38(31) 38-lead plastic tssop 38 37 36 34 32 30 28 26 24 22 21 20 39 gnd intv cc mode imon_in shdn csn csp ldo33 fbin fbout imon_out v c ss clkout sync rt gnd bg1 gatev cc bg2 v in cspin csnin cspout csnout extv cc boost1 tg1 sw1 sw2 tg2 boost2 t jmax = 125c, ja = 25c/w exposed pad (pin 39) is gnd, must be soldered to pcb http:///
LT8705 3 8705p for more information www.linear.com/8705 electrical characteristics parameter conditions min typ max units voltage supplies and regulators v in operating voltage range extv cc = 0v extv cc = 7.5v l l 5.5 2.8 80 80 v v v in quiescent current not switching, v extvcc = 0 2.65 4.2 ma v in quiescent current in shutdown v shdn = 0v 0 1 a extv cc switchover voltage i intvcc = 20ma, v extvcc rising l 6.15 6.4 6.6 v extv cc switchover hysteresis 0.18 v intv cc current limit maximum current draw from intv cc and ldo33 pins combined. regulated from v in or extv cc (12v) intv cc = 5.25v intv cc = 4.5v l l 90 28 127 42 165 55 ma ma intv cc voltage regulated from v in , i intvcc = 20ma regulated from extv cc (12v), i intvcc = 20ma l l 6.15 6.15 6.35 6.35 6.55 6.55 v v intv cc load regulation i intvcc = 0ma to 50ma C0.5 C1.5 % intv cc , gatev cc undervoltage lockout intv cc falling, gatev cc connected to intv cc l 4.45 4.65 4.85 v intv cc , gatev cc undervoltage lockout hysteresis gatev cc connected to intv cc 160 mv intv cc regulator dropout voltage v in -v intvcc , i intvcc = 20ma 245 mv ldo33 pin voltage 5ma from ldo33 pin l 3.23 3.295 3.35 v ldo33 pin load regulation i ldo33 = 0.1ma to 5ma C0.25 C1 % ldo33 pin current limit l 12 17.25 22 ma ldo33 pin undervoltage lockout ldo33 falling 2.96 3.04 3.12 v ldo33 pin undervoltage lockout hysteresis 35 mv switching regulator control maximum current sense threshold (v csp C v csn ) boost mode, minimum m3 switch duty cycle l 102 117 132 mv maximum current sense threshold (v csn C v csp ) buck mode, minimum m2 switch duty cycle l 69 86 102 mv gain from v c to maximum current sense voltage (v csp -v csn ) (a5 in the block diagram) boost mode buck mode 150 C150 mv/v mv/v shdn input voltage high shdn rising to enable the device l 1.184 1.234 1.284 v shdn input voltage high hysteresis 50 mv shdn input voltage low device disabled, low quiescent current l 0.35 v the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, shdn = 3v unless otherwise noted. (note 3) order information lead free finish tape and reel part marking* package description temperature range LT8705euhf#pbf LT8705euhf#trpbf 8705 38-lead (5mm 7mm) plastic qfn C40c to 125c LT8705iuhf#pbf LT8705iuhf#trpbf 8705 38-lead (5mm 7mm) plastic qfn C40c to 125c LT8705efe#pbf LT8705efe#trpbf LT8705fe 38-lead plastic tssop C40c to 125c LT8705ife#pbf LT8705ife#trpbf LT8705fe 38-lead plastic tssop C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ http:///
LT8705 4 8705p for more information www.linear.com/8705 parameter conditions min typ max units shdn pin bias current v shdn = 3v v shdn = 12v 0 11 1 22 a a swen rising threshold voltage (note 5) l 1.156 1.206 1.256 v swen threshold voltage hysteresis (note 5) 22 mv mode pin forced continuous mode threshold l 0.4 v mode pin burst mode range l 1.0 1.7 v mode pin discontinuous mode threshold l 2.3 v soft-start charging current v ss = 0.5v 13 19 25 a soft-start discharge current v ss = 0.5v 9.5 a voltage regulator loops (refer to block diagram to locate amplifiers) regulation voltage for fbout v c = 1.2v l 1.193 1.207 1.217 v regulation voltage for fbin v c = 1.2v l 1.187 1.205 1.220 v line regulation for fbout and fbin error amp reference voltage v in = 12v to 80v 0.002 0.005 %/v fbout pin bias current current out of pin 15 na fbout error amp ea4 g m 315 mho fbout error amp ea4 voltage gain 220 v/v fbin pin bias current current out of pin 10 na fbin error amp ea3 g m 130 mho fbin error amp ea3 voltage gain 90 v/v srvo_fbin activation threshold (note 5) (v fbin falling) C (regulation voltage for fbin), v fbout = v imon_in = v imon_out = 0v 56 72 89 mv srvo_fbin activation threshold hysteresis (note 5) v fbout = v imon_in = v imon_out = 0v 33 mv srvo_fbout activation threshold (note 5) (v fbout rising) C (regulation voltage for fbout), v fbin = 3v, v imon_in = v imon_out = 0v C37 C29 C21 mv srvo_fbout activation threshold hysteresis (note 5) v fbin = 3v, v imon_in = 0v, v imon_out = 0v 15 mv srvo_fbin, srvo_fbout low voltage (note 5) i = 100a l 110 330 mv srvo_fbin, srvo_fbout leakage current (note 5) v srvo_fbin = v srvo_fbout = 2.5v l 0 1 a current regulation loops (refer to block diagram to locate amplifiers) regulation voltages for imon_in and imon_out v c = 1.2v l 1.191 1.208 1.223 v line regulation for imon_in and imon_out error amp reference voltage v in = 12v to 80v 0.002 0.005 %/v cspin, csnin bias current boost capacitor charge control block not active i cspin + i csnin , v cspin = v csnin = 12v 31 a cspin, csnin common mode operating voltage range l 1.5 80 v cspin, csnin differential operating voltage range l C100 100 mv v cspin-csnin to imon_in amplifier a7 g m v cspin C v csnin = 50mv, v cspin = 5.025v l 0.95 0.94 1 1 1.05 1.06 mmho mmho imon_in maximum output current l 100 a imon_in overvoltage threshold l 1.55 1.61 1.67 v imon_in error amp ea2 g m 185 mho imon_in error amp ea2 voltage gain 130 v/v electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, shdn = 3v unless otherwise noted. (note 3) http:///
LT8705 5 8705p for more information www.linear.com/8705 parameter conditions min typ max units cspout, csnout bias current boost capacitor charge control block not active i cspout + i csnout , v cspout = v csnout = 12v i cspout + i csnout , v cspout = v csnout = 1.5v 45 4 a a cspout, csnout common mode operating voltage range l 0 80 v cspout, csnout differential mode operating voltage range l C100 100 mv v cspout-csnout to imon_out amplifier a6 g m v cspout C v csnout = 50mv, v cspout = 5.052v v cspout C v csnout = 50mv, v cspout = 5.025v v cspout C v csnout = 5mv, v cspout = 5.0025v v cspout C v csnout = 5mv, v cspout = 5.0025v l l 0.95 0.94 0.65 0.55 1 1 1 1 1.05 1.085 1.35 1.6 mmho mmho mmho mmho imon_out maximum output current l 100 a imon_out overvoltage threshold l 1.55 1.61 1.67 v imon_out error amp ea1 g m 185 mho imon_out error amp ea1 voltage gain 130 v/v srvo_iin activation threshold (note 5) (v imon_in rising) C (regulation voltage for imon_in), v fbin = 3v, v fbout = 0v, v imon_out = 0v C60 C49 C37 mv srvo_iin activation threshold hysteresis (note 5) v fbin = 3v, v fbout = 0v, v imon_out = 0v 22 mv srvo_iout activation threshold (note 5) (v imon_out rising) C (regulation voltage for imon_ out), v fbin = 3v, v fbout = 0v, v imon_in = 0v C62 C51 C39 mv srvo_iout activation threshold hystersis (note 5) v fbin = 3v, v fbout = 0v, v imon_in = 0v 22 mv srvo_iin, srvo_iout low voltage (note 5) i = 100a l 110 330 mv srvo_iin, srvo_iout leakage current (note 5) v srvo_iin = v srvo_iout = 2.5v l 0 1 a nmos gate drivers tg1, tg2 rise time c load = 3300pf (note 4) 20 ns tg1, tg2 fall time c load = 3300pf (note 4) 20 ns bg1, bg2 rise time c load = 3300pf (note 4) 20 ns bg1, bg2 fall time c load = 3300pf (note 4) 20 ns tg1 off to bg1 on delay c load = 3300pf each driver 100 ns bg1 off to tg1 on delay c load = 3300pf each driver 80 ns tg2 off to bg2 on delay c load = 3300pf each driver 100 ns bg2 off to tg2 on delay c load = 3300pf each driver 80 ns minimum on-time for main switch in boost operation (t on(m3,min) ) switch m3, c load = 3300pf 265 ns minimum on-time for synchronous switch in buck operation (t on(m2,min) ) switch m2, c load = 3300pf 260 ns minimum off-time for main switch in steady-state boost operation switch m3, c load = 3300pf 245 ns minimum off-time for synchronous switch in steady-state buck operation switch m2, c load = 3300pf 245 ns oscillator switch frequency range syncing or free running 100 400 khz switching frequency, f osc r t = 365k r t = 215k r t = 124k l l l 102 170 310 120 202 350 142 235 400 khz khz khz electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, shdn = 3v unless otherwise noted. (note 2) http:///
LT8705 6 8705p for more information www.linear.com/8705 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: do not force voltage on the v c pin. note 3: the LT8705e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LT8705i is guaranteed over the full C40c to 125c junction temperature range. note 4: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 5: this specification not applicable in the fe38 package. note 6: do not apply a voltage or current source to these pins. they must be connected to capacitive loads only, otherwise permanent damage may occur. note 7: negative voltages on the sw1 and sw2 pins are limited, in an application, by the body diodes of the external nmos devices, m2 and m3, or parallel schottky diodes when present. the sw1 and sw2 pins are tolerant of these negative voltages in excess of one diode drop below ground, guaranteed by design. parameter conditions min typ max units sync high level for synchronization l 1.3 v sync low level for synchronization l 0.5 v sync clock pulse duty cycle v sync = 0v to 2v 20 80 % recommended minimum sync ratio f sync /f osc 3/4 clkout output voltage high 1ma out of clkout pin 2.3 2.45 2.55 v clkout output voltage low 1ma into clkout pin 25 100 mv clkout duty cycle t j = C40c t j = 25c t j = 125c 21.4 42.5 75 % % % clkout rise time c load = 200pf 30 ns clkout fall time c load = 200pf 25 ns clkout phase delay sync rising to clkout rising, f osc = 100khz l 160 180 200 deg electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, shdn = 3v unless otherwise noted. (note 3) http:///
LT8705 7 8705p for more information www.linear.com/8705 typical performance characteristics fbout voltages (five parts) feedback voltages oscillator frequency maximum inductor current sense voltage vs duty cycle inductor current sense voltage at minimum duty cycle efficiency vs output current (boost region-figure 14) efficiency vs output current (buck-boost region-figure 14) efficiency vs output current (buck region-figure 14) load current (ma) 10 0 efficiency (%) 20 30 40 50 60 70 100 1000 8705 g01 80 90 100 v in = 36v v out = 48v 10 10000 burst ccm dcm load current (ma) 10 0 efficiency (%) 20 30 40 50 60 70 100 1000 8705 g02 80 90 100 v in = 48v v out = 48v 10 10000 burst ccm dcm load current (ma) 10 0 efficiency (%) 20 30 40 50 60 70 100 1000 8705 g03 80 90 100 v in = 72v v out = 48v 10 10000 burst ccm dcm temperature (c) ?55 1.17 pin voltage (v) 1.18 1.19 1.20 1.21 ?5 45 95 145 8705 g04 1.22 1.23 ?30 20 70 120 imon_out imon_in fbout fbin v c = 1.2v temperature (c) ?50 fbout voltage (v) 1.21 1.22 1.23 25 75 8795 g05 1.20 1.19 ?25 0 50 100 150125 1.18 1.17 v c = 1.2v temperature (c) ?40 frequency (khz) 200 300 120 8705 g06 100 0 0 40 80 ?20 20 60 100 400 r t = 124k r t = 215k r t = 365k 150 250 50 350 m2 or m3 duty cycle (%) 0 100 120 140 80 8705 g07 80 60 20 40 60 100 40 20 0 |csp-csn| (mv) buck region boost region v c (v) 0.5 ?80 csn-csp (mv) csp-csn (mv) ?40 ?20 0 20 40 60 1 1.5 8705 g08 80 100 120 buck region boost region ?60 ?80 ?40 ?20 0 20 40 60 80 100 120 ?60 2 maximum inductor current sense voltage at minimum duty cycle temperature (c) ?40 0 |csp-csn| (mv) 20 40 60 80 100 120 0 40 80 ?20 20 60 100 120 8705 g09 boost region buck region t a = 25c unless otherwise specified. http:///
LT8705 8 8705p for more information www.linear.com/8705 typical performance characteristics imon output currents clkout duty cycle ldo33 pin regulation (i ldo33 = 1ma) shdn and swen pin thresholds vs temperature intv cc line regulation (extv cc = 0v) intv cc line regulation (v in = 12v) maximum v c vs ss minimum inductor current sense voltage in forced continuous mode v in supply current vs voltage (not switching) m2 or m3 duty cycle (%) 0 ?40 ?20 0 80 8705 g10 ?60 ?80 20 40 60 100 ?100 ?120 ?140 ?|csp-csn| (mv) buck region boost region v in (v) 4 4.0 intv cc (v) 4.5 5.0 5.5 6.0 8 12 16 20 8705 g11 6.5 7.0 6 10 14 18 extv cc (v) 4 5.5 intv cc (v) 6.0 6.5 7.0 6 8 8705 g12 10 12 extv cc rising extv cc falling ss (v) 0 0 maximum v c (v) 0.2 0.6 0.8 1.0 2.0 1.4 0.4 0.8 1.0 1.2 8705 g13 0.4 1.6 1.8 1.2 0.2 0.6 1.4 boost and buck-boost regions buck region t j = 25c v in (v) 5 i in (ma) 2.0 2.5 3.0 65 75 35 45 55 8705 g14 1.5 1.0 15 25 0.5 0 3.5 gatev cc connected to intv cc 125c 25c ?40c cspin-csnin (mv) cspout-csnout (mv) ?100 ?25 imon_out, imon_in (a) 0 50 75 100 100 200 8705 g15 25 0 ?50 150 50 200 125 150 175 temperature (c) ?50 duty cycle (%) 60 80 100 25 75 150 8705 g16 40 20 0 ?25 0 50 100 125 intv cc (v) 2.5 ldo (v) 2.5 3.0 6 8705 g17 2.0 1.5 3 4 3.5 4.5 5 5.5 3.5 125c 25c ?40c temperature (c) ?55 pin threshold voltage (v) 1.22 1.26 1.30 125 8705 g18 1.18 1.14 1.20 1.24 1.28 1.16 1.12 1.10 ?15 25 65 85 ?35 145 5 45 105 rising falling shdn swen t a = 25c unless otherwise specified. http:///
LT8705 9 8705p for more information www.linear.com/8705 typical performance characteristics discontinuous mode (figure 14) forced continuous mode (figure 14) forced continuous mode (figure 14) forced continuous mode (figure 14) shdn and mode pin currents internal v in uvlo srvo_xx pin activation thresholds srvo_xx pin activation threshold hysteresis pin voltage (v) 0 current into pin (a) 10 14 18 24 8705 g19 6 2 8 12 16 4 0 ?2 63 129 18 21 27 15 30 mode shdn temperature (c) ?40 ?20 0 v in uvlo (v) 0.5 1.0 1.5 2.0 2.5 3.0 0 20 40 60 80 100 120 8705 g20 temperature (c) ?50 v pin -v regulation v pin approaching v regulation (mv) 25 75 150 8705 g21 ?25 ?75 0 50 100 ?25 25 75 125 125 0 50 ?50 100 fbin fbout imon_in imon_out temperature (c) ?50 pin activation threshold hystersis (mv) 30 40 50 25 75 150 8705 g22 20 10 0 ?25 0 50 100 125 fbin fbout imon_in imon_out sw1 50v/div sw2 50v/div i l 2a/div 5s/div v in = 72v v out = 48v 8705 g23 sw1 20v/div sw2 20v/div i l 2a/div 5s/div v in = 36v v out = 48v 8705 g24 sw1 20v/div sw2 20v/div i l 2a/div 5s/div v in = 48v v out = 48v 8705 g25 sw1 20v/div sw2 20v/div i l 2a/div 5s/div v in = 72v v out = 48v 8705 g26 t a = 25c unless otherwise specified. http:///
LT8705 10 8705p for more information www.linear.com/8705 typical performance characteristics load step (figure 14) load step (figure 14) load step (figure 14) line transient (figure 14) line transient (figure 14) burst mode operation (figure 14) burst mode operation (figure 14) v out 100mv/div i l 1a/div 2ms/div v in = 36v v out = 48v 8705 g27 v out 100mv/div i l 5a/div 5ms/div v in = 72v v out = 48v 8705 g28 v out 500mv/div i l 2a/div 500s/div v in = 36v v out = 48v load step = 1a to 3a 8705 g29 v out 500mv/div i l 2a/div 500s/div v in = 48v v out = 48v load step = 1a to 3a 8705 g30 v out 500mv/div i l 2a/div 500s/div v in = 48v v out = 48v load step = 1a to 3a 8705 g30 v out 500mv/div i l 2a/div 500s/div v in = 72v v out = 48v load step = 1a to 3a 8705 g31 v out 0.5v/div v c 0.5v/div v in 36v to 72v i l 2a/div 2ms/div 8705 g32 v out 0.5v/div v c 0.5v/div v in 72v to 36v i l 2a/div 2ms/div 8705 g33 t a = 25c unless otherwise specified. http:///
LT8705 11 8705p for more information www.linear.com/8705 pin functions shdn (pin 1/pin 4): shutdown pin. tie high to enable device. ground to shut down and reduce quiescent current to a minimum. do not float this pin. csn (pin 2/pin 5): the (C) input to the inductor current sense and reverse-current detect amplifier. csp (pin 3/pin 6): the (+) input to the inductor current sense and reverse-current detect amplifier. the v c pin voltage and built-in offsets between csp and csn pins, in conjunction with the r sense resistor value, set the current trip threshold. ldo33 (pin 4/pin7): 3.3v regulator output. bypass this pin to ground with a minimum 0.1f ceramic capacitor. fbin (pin 5/pin 8): input feedback pin. this pin is con - nected to the input error amplifier input. fbout (pin 6/pin 9): output feedback pin. this pin connects the error amplifier input to an external resistor divider from the output. imon_out (pin 7/pin 10): output current monitor pin. the current out of this pin is proportional to the output current. see the operation and applications information sections. v c (pin 8/pin 11): error amplifier output pin. tie external compensation network to this pin. ss (pin 9/pin 12): soft-start pin. place at least 100nf of capacitance here. upon start-up, this pin will be charged by an internal resistor to 2.5v. clkout (pin 10/pin 13): clock output pin. use this pin to synchronize one or more compatible switching regulator ics to the LT8705. clkout toggles at the same frequency as the internal oscillator or as the sync pin, but is ap - proximately 180 out of phase. clkout may also be used as a temperature monitor since the clkout duty cycle varies linearly with the parts junction temperature. the clkout pin can drive capacitive loads up to 200pf. sync (pin 11/pin 14): to synchronize the switching fre - quency to an outside clock, simply drive this pin with a clock. the high voltage level of the clock needs to exceed 1.3v, and the low level should be less than 0.5v. drive this pin to less than 0.5v to revert to the internal free-running clock. see the applications information section for more information. (qfn/tssop) rt (pin 12/pin 15): timing resistor pin. adjusts the switch - ing frequency. place a resistor from this pin to ground to set the free-running frequency. do not float this pin. bg1, bg2 (pins 14, 16/pins 17, 19): bottom gate drive. drives the gates of the bottom n-channel mosfets be - tween ground and gatev cc . gatev cc (pin 15/pin 18): power supply for gate drivers. must be connected to the intv cc pin. do not power from any other supply. locally bypass to gnd. boost1, boost2 (pins 23, 17/pins 28, 20): boosted floating driver supply. the (+) terminal of the bootstrap capacitor connects here. the boost1 pin swings from a diode voltage below gatev cc up to v in + gatev cc . the boost2 pin swings from a diode voltage below gatev cc up to v out + gatev cc tg1, tg2 (pins 22, 18/pins 26, 21): top gate drive. drives the top n-channel mosfets with voltage swings equal to gatev cc superimposed on the switch node voltages. sw1, sw2 (pins 21, 19/pins 24, 22): switch nodes. the (C) terminals of the bootstrap capacitors connect here. srvo_fbin (pin 25 qfn only): open-drain logic out - put. this pin is pulled to ground when the input voltage feedback loop is active. srvo_iin (pin 26 qfn only): open-drain logic output. the pin is pulled to ground when the input current loop is active. srvo_iout (pin 27 qfn only): open-drain logic out - put. the pin is pulled to ground when the output current feedback loop is active. srvo_fbout (pin 28 qfn only): open-drain logic out - put. this pin is pulled to ground when the output voltage feedback loop is active. extv cc (pin 29/pin 30): external v cc input. when extv cc exceeds 6.4v (typical), intv cc will be powered from this pin. when extv cc is lower than 6.22v (typical), intv cc will be powered from v in . csnout (pin 30/pin 32): the (C) input to the output cur - rent monitor amplifier. connect this pin to v out when not in use. see applications information section for proper use of this pin. http:///
LT8705 12 8705p for more information www.linear.com/8705 cspout (pin 31/pin 34): the (+) input to the output current monitor amplifier. this pin and the csnout pin measure the voltage across the sense resistor, r sense2 , to provide the output current signals. connect this pin to v out when not in use. see applications information section for proper use of this pin. csnin (pin 32/pin 36): the (C) input to the input current monitor amplifier. this pin and the cspin pin measure the voltage across the sense resistor, r sense1 , to provide the input current signals. connect this pin to v in when not in use. see applications information section for proper use of this pin. cspin (pin 33/pin 37): the (+) input to the input cur - rent monitor amplifier. connect this pin to v in when not in use. see applications information section for proper use of this pin. v in (pin 34/pin 38): main input supply pin. it must be locally bypassed to ground. intv cc (pin 35/pin 1): internal 6.35v regulator output. must be connected to the gatev cc pin. intv cc is powered from extv cc when the extv cc voltage is higher than 6.4v, otherwise intv cc is powered from v in . bypass this pin to ground with a minimum 4.7f ceramic capacitor. swen (pin 36 qfn only): switch enable pin. tie high to enable switching. ground to disable switching. dont float this pin. this pin is internally tied to intv cc in the tssop package. imon_in (pin 38/pin 3): input current monitor pin. the current out of this pin is proportional to the input current. see the operation and applications information sections. mode (pin 37/pin 2): mode pin. the voltage applied to this pin sets the operating mode of the controller. when the applied voltage is less than 0.4v, the forced continu - ous current mode is active. when this pin is allowed to float, burst mode operation is active. when the mode pin voltage is higher than 2.3v, discontinuous mode is active. gnd (pin 13, exposed pad pin 39/pin 16, exposed pad pin 39): ground. tie directly to local ground plane. pin functions (qfn/tssop) http:///
LT8705 13 8705p for more information www.linear.com/8705 block diagram figure 1. block diagram v in csnin r sense1 r sense r sense2 v out v in csn csp cspin imon_in mode clkout sync rt ss 2.5v extv cc r shdn2 intv cc boost1 tg1 c b1 m1 m2 m3 d1 (opt) d2 (opt) m4 c b2 d b2 d b1 sw1 gatev cc bg1 gnd bg2 sw2 tg2 boost2 cspout csnout imon_out fbin r fbin1 r fbout1 r fbout2 r fbin2 fbout v c swen osc fault_int startup and fault logic ? + 8705 f01 a7 shdn 1.234v ? + ? + a5 uv_intv cc ot oi_in oi_out uv_v in uv_ldo33 uv_gatev cc 6.35v ldo reg 6.35v ldo reg 3.3v ldo reg 6.4v en en internal supply2 internal supply1 v in ? + ? + ? + buck logic boost capacitor charge control boost logic ldo reg ? + a6 srvo_fbout srvo_fbin srvo_iout srvo_iin ldo33 ? + ea4 ? + ea3 ? + ea2 1.205v 1.207v 1.208v imon_in ? + ea1 v in r shdn1 a8 a9 http:///
LT8705 14 8705p for more information www.linear.com/8705 operation refer to the block diagram (figure 1) when reading the following sections about the operation of the LT8705. main control loop the LT8705 is a current mode controller that provides an output voltage above, equal to or below the input voltage. the ltc proprietary topology and control architecture employs a current-sensing resistor (r sense ) in buck or boost modes. the inductor current is controlled by the voltage on the v c pin, which is the diode-and of error amplifiers ea1-ea4. in the simplest form, where the output is regulated to a constant voltage, the fbout pin receives the output voltage feedback signal, which is compared to the internal reference voltage by ea4. low output voltages would create a higher v c voltage, and thus more current would flow into the output. conversely, higher output volt - ages would cause v c to drop, thus reducing the current fed into the output. the LT8705 contains four error amplifiers (ea1-ea4) al - lowing it to regulate or limit the output current (ea1), input current (ea2), input voltage (ea3) and/or output voltage (ea4). in a typical application, the output voltage might be regulated using ea4, while the remaining error amplifiers are monitoring for excessive input or output current or an input undervoltage condition. in other applications, such as a battery charger, the output current regulator (ea1) can facilitate constant current charging until a predetermined voltage is reached where the output voltage (ea4) control would take over. intv cc /extv cc /gatev cc /ldo33 power power for the top and bottom mosfet drivers, the ldo33 pin and most internal circuitry is derived from the intv cc pin. intv cc is regulated to 6.35v (typical) from either the v in or extv cc pin. when the extv cc pin is left open or tied to a voltage less than 6.22v (typical), an internal low dropout regulator regulates intv cc from v in . if extv cc is taken above 6.4v (typical), another low dropout regula - tor will instead regulate intv cc from extv cc . regulating intv cc from extv cc allows the power to be derived from the lowest supply voltage (highest efficiency) such as the LT8705 switching regulator output (see intv cc regulators and extv cc connection in the applications information section for more details). the gatev cc pin directly powers the bottom mosfet drivers for switches m2 and m3. gatev cc should always be connected to intv cc and should not be powered or connected to any other source. undervoltage lock outs (uvlos) monitoring intv cc and gatev cc disable the switching regulator when the pins are below 4.65v (typical). the ldo33 pin is available to provide power to external components such as a microcontroller and/or to provide an accurate bias voltage. load current is limited to 17.25ma (typical). as long as shdn is high the ldo33 output is linearly regulated from the intv cc pin and is not affected by the intv cc or gatev cc uvlos or the swen pin volt - age. ldo33 will remain regulated as long as shdn is high and sufficient voltage is available on intv cc (typically > 4.0v). an undervoltage lockout, monitoring ldo33, will disable the switching regulator when ldo33 is below 3.04v (typical). start-up figure 2 illustrates the start-up sequence for the LT8705. the master shutdown pin for the chip is shdn . when driven below 0.4v the chip is disabled (chip off state) and quiescent current is minimal. increasing the shdn voltage can increase quiescent current but will not enable the chip until shdn is driven above 1.234v (typical) after which the intv cc and ldo33 regulators are enabled (switcher off state). external devices powered by the ldo33 pin can become active at this time if enough voltage is available on v in or extv cc to raise intv cc , and thus ldo33, to an adequate voltage. starting up the switching regulator happens after swen (switcher enable) is also driven above 1.206v (typical), intv cc and gatev cc have risen above 4.81v (typical) and the ldo33 pin has risen above 3.08v (typical) (initialize state). the swen pin is not available in the tssop pack - age. in this package the swen pin is internally connected to intv cc . start-up: soft-start of switch current in the initialize state, the ss (soft-start) pin is pulled low to prepare for soft starting the regulator. if forced continu - ous mode is selected (mode pin low), the part is put into discontinuous mode during soft-start to prevent current http:///
LT8705 15 8705p for more information www.linear.com/8705 operation t junction < 160c and shdn > 1.234v and v in > 2.5v and (swen* < 1.184v or (intv cc and gatev cc < 4.65v) or ldo33 < 3.04v) soft-start ? ss charges up ? switcher enabled ? ss slowly discharges switcher off ? switcher disabled ? intv cc and ldo33 outputs enabled normal mode post fault delay ? ss charges up ? switcher disabled ? clkout disabled fault detected ? normal operation ? when ss > 1.6v ... ? clkout enabled ? enable forced continuous mode if selected initialize ss < 50mv fault fault fault ss < 50mv *swen is connected to intv cc in the tssop package 8705 f02 fault ? ss pulled low ? force discontinous mode unless burst mode operation selected chip off typical values shdn < 1.184v or v in < 2.5v or t junction > 165c ? switcher off ? ldos off typical values shdn > 1.234v and v in > 2.5v and swen* > 1.206v and (intv cc and gatev cc > 4.81v) and ldo33 > 3.075v ss > 1.6v and no fault conditions still detected typical values fault = overvoltage (imon_in or imon_out > 1.61v typ) figure 2. start-up and fault sequence from being drawn out of the output and forced into the input. after ss has been discharged to less than 50mv, a soft-start of the switching regulator begins (soft-start state). the soft-start circuitry provides for a gradual ramp-up of the inductor current by gradually allowing the v c voltage to rise (refer to v c vs ss voltage in the typical performance characteristics). this prevents abrupt surges of current from being drawn out of the input power sup - ply. an integrated 100k resistor pulls the ss pin to ? 2.5v. the ramp rate of the ss pin voltage is set by this 100k resistor and the external capacitor connected to this pin. once ss gets to 1.6v, the clkout pin is enabled, the part is allowed to enter forced continuous mode (if mode is low) and an internal regulator pulls ss up quickly to ? 2.5v. typical values for the external soft-start capacitor range from 100nf to 1f. a minimum of 100nf is recommended. fault conditions the LT8705 activates a fault sequence under certain op - erating conditions. if any of these conditions occur (see figure?2) the clkout pin and internal switching activity are disabled. at the same time, a timeout sequence com - mences where the ss pin is charged up to a minimum of 1.6v (fault detected state). the ss pin will continue http:///
LT8705 16 8705p for more information www.linear.com/8705 operation operation charging up to 2.5v and be held there in the case of a fault event that persists. after the fault condition had ended and ss is greater than 1.6v, ss will then slowly discharge to 50mv (post fault delay state). this timeout period relieves the part and other downstream power components from electrical and thermal stress for a minimum amount of time as set by the voltage ramp rate on the ss pin. after ss has discharged to < 50mv, the LT8705 will enter the soft-start state and restart switching activity. power switch control figure 3 shows a simplified diagram of how the four power switches are connected to the inductor, v in , v out and ground. figure 4 shows the regions of operation for the LT8705 as a function of v out -v in or switch duty cycle dc. the power switches are properly controlled so the transfer between modes is continuous. is turned on first. inductor current is sensed by amplifier a5 while switch m2 is on. a slope compensation ramp is added to the sensed voltage which is then compared by a8 to a reference that is proportional to v c . after the sensed inductor current falls below the reference, switch m2 is turned off and switch m1 is turned on for the remainder of the cycle. switches m1 and m2 will alternate, behaving like a typical synchronous buck regulator. tg1 bg1 tg2 bg2 r sense 8705 f03 m1 m2 m4 m3 l sw1 sw2 v in v out m1 on, m2 off pwm m3, m4 switches m4 on, m3 off pwm m1, m2 switches 4-switch pwm v out -v in switch m3 dc max switch m2 dc max switch m3 dc min switch m2 dc min boost region buck region 0 buck/boost region 8705 f04 figure 3. simplified diagram of the output switches figure 4. operating regions vs v out -v in switch m1 clock switch m2 switch m3 switch m4 i l off on 8705 f05 figure 5. buck region (v in >> v out ) the part will continue operating in the buck region over a range of switch m2 duty cycles. the duty cycle of switch?m2 in the buck region is given by: dc (m2,buck) = 1? v out v in ? ? ? ? ? ? ? 100% as v in and v out get closer to each other, the duty cycle decreases until the minimum duty cycle of the converter in buck mode reaches dc (absmin,m2,buck) . if the duty cycle becomes lower than dc (absmin,m2,buck) the part will move to the buck-boost region. dc (absmin,m2,buck) ? t on(m2,min) ? f ? 100% where: t on(m2,min) is the minimum on-time for the synchronous switch in buck operation (260ns typical, see electrical characteristics). f is the switching frequency when v in is much higher than v out the duty cycle of switch m2 will increase, causing the m2 switch off-time to decrease. the m2 switch off-time should be kept above 245ns (typical, see electrical characteristics) to maintain steady-state operation, avoid duty cycle jitter, increased output ripple and reduction in maximum output current. power switch control: buck region (v in >> v out ) when v in is significantly higher than v out , the part will run in the buck region. in this region switch m3 is always off. also, switch m4 is always on unless reverse current is detected while in burst mode operation or discontinuous mode. at the start of every cycle, synchronous switch m2 http:///
LT8705 17 8705p for more information www.linear.com/8705 operation operation power switch control: buck-boost (v in ? v out ) when v in is close to v out , the controller enters the buck- boost region. figure 6 shows typical waveforms in this region. every cycle, if the controller starts with switches?m2 and m4 turned on, the controller first operates as if in the buck region. when a8 trips, switch m2 is turned off and m1 is turned on until the middle of the clock cycle. next, switch?m4 turns off and m3 turns on. the LT8705 then operates as if in boost mode until a9 trips. finally switch m3 turns off and m4 turns on until the end of the cycle. if the controller starts with switches m1 and m3 turned on, the controller first operates as if in the boost region. when a9 trips, switch m3 is turned off and m4 is turned on until the middle of the clock cycle. next, switch m1 turns off and m2 turns on. the LT8705 then operates as if in buck mode until a8 trips. finally switch m2 turns off and m1 turns on until the end of the cycle. power switch control: boost region (v in << v out ) when v out is significantly higher than v in , the part will run in the boost region. in this region switch m1 is always on and switch m2 is always off. at the start of every cycle, switch m3 is turned on first. inductor current is sensed by amplifier a5 while switch m3 is on. a slope compensation ramp is added to the sensed voltage which is then compared (a9) to a reference that is proportional to v c . after the sensed inductor current rises above the reference voltage, switch m3 is turned off and switch m4 is turned on for the remainder of the cycle. switches m3 and m4 will alternate, behaving like a typical synchronous boost regulator. the part will continue operating in the boost region over a range of switch m3 duty cycles. the duty cycle of switch?m3 in the boost region is given by: dc (m3,boost) = 1? v in v out ? ? ? ? ? ? ? 100% as v in and v out get closer to each other, the duty cycle decreases until the minimum duty cycle of the converter in boost mode reaches dc (absmin,m3,boost) . if the duty cycle becomes lower than dc (absmin,m3,boost) the part will move to the buck-boost region: dc (absmin,m3,boost) ? t on(m3,min) ? f ? 100% where: t on(m3,min) is the minimum on-time for the main switch in boost operation (265ns typical, see electrical char - acteristics) f is the switching frequency switch m1 clock switch m2 switch m3 switch m4 i l 8705 f06a switch m1 clock switch m2 switch m3 switch m4 i l 8705 f06b (6a) buck-boost region (v in v out ) (6b) buck-boost region (v in v out ) figure 6. buck-boost region figure 7. boost region (v in << v out ) switch m1 clock switch m2 switch m3 switch m4 i l off on 8705 f07 http:///
LT8705 18 8705p for more information www.linear.com/8705 operation when v out is much higher than v in the duty cycle of switch m3 will increase, causing the m3 switch off-time to decrease. the m3 switch off-time should be kept above 245ns (typical, see electrical characteristics) to maintain steady-state operation, avoid duty cycle jitter, increased output ripple and reduction in maximum output current. light load current operation (mode pin) under light current load conditions, the LT8705 can be set to operate in discontinuous mode, forced continuous mode, or burst mode operation. to select forced continuous mode, tie the mode pin to a voltage below 0.4v (i.e., ground). to select discontinuous mode, tie mode to a voltage above 2.3v (i.e., ldo33). to select burst mode operation, float the mode pin or tie it between 1.0v and 1.7v. discontinuous mode: when the LT8705 is in discontinu - ous mode, synchronous switch m4 is held off whenever reverse current in the inductor is detected. this is to prevent current draw from the output and/or feeding current to the input supply. under very light loads, the current compara - tor may also remain tripped for several cycles and force switches m1 and m3 to stay off for the same number of cycles (i.e., skipping pulses). synchronous switch m2 will remain on during the skipped cycles, but since switch m4 is off, the inductor current will not reverse. burst mode operation: burst mode operation sets a v c level, with about 25mv of hysteresis, below which switching activity is inhibited and above which switching activity is re-enabled. a typical example is when, at light output currents, v out rises and forces the v c pin below the threshold that temporarily inhibits switching. after v out drops slightly and v c rises ~25mv the switching is resumed, initially in the buck-boost region. burst mode operation can increase efficiency at light load currents by eliminating unnecessary switching activity and related power losses. burst mode operation handles reverse-current detection similar to discontinuous mode. the m4 switch is turned off when reverse current is detected. forced continuous mode: the forced continuous mode allows the inductor current to reverse directions without any switches being forced off to prevent this from hap - pening. at very light load currents the inductor current will swing positive and negative as the appropriate aver - age current is delivered to the output. during soft-start, when the ss pin is below 1.6v, the part will be forced into discontinuous mode to prevent pulling current from the output to the input. after ss rises above 1.6v, forced continuous mode will be enabled. voltage regulation loops the LT8705 provides two constant-voltage regulation loops, one for output voltage and one for input voltage. a resistor divider between v out , fbout and gnd senses the output voltage. as with traditional voltage regulators, when fbout rises near or above the reference voltage of ea4 (1.207v typical, see block diagram), the v c voltage is reduced to command the amount of current that keeps v out regulated to the desired voltage. the input voltage can also be sensed by connecting a resistor divider between v in , fbin and gnd. when the fbin voltage falls near or below the reference voltage of ea3 (1.205v typical, see block diagram), the v c voltage is reduced to also reduce the input current. for applications with a high input source impedance (i.e., a solar panel), the input voltage regulation loop can prevent the input voltage from becoming too low under high output load conditions. for applications with a lower input source impedance (i.e., batteries and voltage supplies), the fbin pin can be used to stop switching activity when the input power supply voltage gets too low for proper system operation. see the applications information section for more information about setting up the voltage regulation loops. current monitoring and regulation the LT8705 provides two constant-current regulation loops, one for input current and one for output current. a sensing resistor close to the input capacitor, sensed by cspin and csnin, monitors the input current. a current, linearly proportional to the sense voltage (v cspin -v csnin ), is forced out of the imon_in pin and into an external re - sistor. the resulting voltage v imon_in is therefore linearly proportional to the input current. similarly, a sensing resistor close to the output capacitor, and sensed by cspout and csnout will monitor the output current and generate a voltage v imon_out that is linearly proportional to the output current. http:///
LT8705 19 8705p for more information www.linear.com/8705 operation when the input or output current causes the respective imon_in or imon_out voltage to rise near or above 1.208v (typical), the v c pin voltage will be pulled down to maintain the desired maximum input and/or output current (see ea1 and ea2 on the block diagram). the input current limit function prevents overloading the dc input source, while the output current limit provides a building block for battery charger or led driver applications. it can also serve as short-circuit protection for a constant-voltage regulator. see the applications information section for more information about setting up the current regulation loops. srvo pins the qfn package has four open-drain srvo pins: srvo_fbin, srvo_fbout, srvo_iin, srvo_iout. place pull-up resistors from the desired srvo pin(s) to a power supply less than 30v (i.e., the ldo33 pin) to enable reading of their logic states. the srvo_fbout, srvo_iin and srvo_iout pins are pulled low when their associ - ated error amp (ea4, ea2, ea1) input voltages are near or greater than their regulation voltages ( ? 1.2v typical). srvo_fbin is pulled low when fbin is near or lower than its regulation voltage ( ? 1.2v typical). the srvo pins can therefore be used as indicators of when their respective feedback loops are active. for example, the srvo_fbout pin pulls low when fbout rises to within 29mv (typical, see electrical characteristics) of its regulation voltage (1.207v typical). the pull-down turns off after fbout falls to more than 44mv (typical) lower than its regulation voltage. as another example, the srvo_iout pin can be read to determine when the output current has nearly reached its predetermined limit. a logic 1 on srvo_iout indicates that the output current has not reached the current limit and a logic 0 indicates that it has. clkout and temperature sensing the clkout pin toggles at the LT8705s internal clock frequency whether the internal clock is synchronized to an external source or is free-running based on the external r t resistor. the clkout pin can be used to synchronize other devices to the LT8705s switching frequency. also, the duty cycle of clkout is proportional to the die temperature and can be used to monitor the die for thermal issues. http:///
LT8705 20 8705p for more information www.linear.com/8705 applications information the first page shows a typical LT8705 application circuit. after the switching frequency is selected, external compo - nent selection continues with the selection of r sense and the inductor value. next, the power mosfets are selected. finally, c in and c out are selected. the following examples and equations assume continuous conduction mode un - less otherwise specified. the circuit can be configured for operation up to an input and/or output voltage of 80v. operating frequency selection the LT8705 uses a constant frequency architecture between 100khz and 400khz. the frequency can be set using the internal oscillator or can be synchronized to an external clock source. selection of the switching frequency is a trade-off between efficiency and component size. low frequency operation increases efficiency by reducing mosfet switching losses, but requires more inductance and/or capacitance to maintain low output ripple voltage. for high power applications, consider operating at lower frequencies to minimize mosfet heating from switching losses. the switching frequency can be set by placing an appropriate resistor from the rt pin to ground and tying the sync pin low. the frequency can also be synchronized to an external clock source driven into the sync pin. the following sections provide more details. internal oscillator the operating frequency of the LT8705 can be set using the internal free-running oscillator. when the sync pin is driven low (<0.5v), the frequency of operation is set by the value of a resistor from the rt pin to ground. an internally trimmed timing capacitor resides inside the ic. the oscillator frequency is calculated using the following formula: f osc = 43,750 r t + 1 ? ? ? ? ? ? khz where f osc is in khz and r t is in k. conversely, r t (in k) can be calculated from the desired frequency (in khz) using: r t = 43,750 f osc ? 1 ? ? ? ? ? ? k ? sync pin and clock synchronization the operating frequency of the LT8705 can be synchronized to an external clock source. to synchronize to the external source, simply provide a digital clock signal into the sync pin. the LT8705 will operate at the sync clock frequency. the duty cycle of the sync signal must be between 20% and 80% for proper operation. also, the frequency of the sync signal must meet the following two criteria: 1. sync may not toggle outside the frequency range of 100khz to 400khz unless it is stopped low to enable the free-running oscillator. 2. the sync pin frequency can always be higher than the free-running oscillator set frequency, f osc , but should not be less than 25% below f osc . after sync begins toggling, it is recommended that switching activity is stopped before the sync pin stops toggling. excess inductor current can result when sync stops toggling as the LT8705 transitions from the external sync clock source to the internal free-running oscillator clock. switching activity can be stopped by driving either the swen or shdn pin low. clkout pin and clock synchronization the clkout pin can drive up to 200pf and toggles at the LT8705s internal clock frequency whether the internal clock is synchronized to the sync pin or is free-running based on the external r t resistor. the rising edge of clkout is approximately 180 out of phase from the internal clocks http:///
LT8705 21 8705p for more information www.linear.com/8705 applications information rising edge or the sync pins rising edge if it is toggling. clkout toggles only in normal mode (see figure 2). the clkout pin can be used to synchronize other de - vices to the LT8705s switching frequency. for example, the clkout pin can be tied to the sync pin of another LT8705 regulator which will operate approximately 180 out of phase of the master LT8705 due to the clkout phase shift. the frequency of the master LT8705 can be set by the external r t resistor or by toggling the sync pin. clkout will begin oscillating after the master LT8705 enters normal mode (see figure 2). note that the rt pin of the slave LT8705 must have a resistor tied to ground. in general, use the same value r t resistor for all of the synchronized LT8705s. the duty cycle of clkout is proportional to the die tem - perature and can be used to monitor the die for thermal issues. see the junction temperature measurement section for more information. inductor current sensing and slope compensation the LT8705 operates using inductor current mode control. as described previously in the power switch control sec - tion, the LT8705 measures the peak of the inductor current waveform in the boost region and the valley of the inductor current waveform in the buck region. the inductor current is sensed across the r sense resistor with pins csp and csn. during any given cycle, the peak (boost region) or valley (buck region) of the inductor current is controlled by the v c pin voltage. slope compensation provides stability in constant- frequency current mode control architectures by prevent - ing subharmonic oscillations at high duty cycles. this is accomplished internally by adding a compensating ramp to the inductor current signal in the boost region, or subtracting a ramp from the inductor current signal in the buck region. at higher duty cycles, this results in a reduction of maximum inductor current in the boost region, and an increase of the maximum inductor current in the buck region. for example, refer to the maximum inductor current sense voltage vs duty cycle graph in the typical performance characteristics section. the graph shows that, with v c at its maximum voltage, the maximum inductor sense voltage v rsense is between 78mv and 117mv depending on the duty cycle. it also shows that the maximum inductor valley current in the buck region is 86mv increasing to ~130mv at higher duty cycles. r sense selection and maximum current the r sense resistance must be chosen properly to achieve the desired amount of output current. too much resistance can limit the output current below the application require - ments. start by determining the maximum allowed r sense resistance in the boost region, r sense(max,boost) . follow this by finding the maximum allowed r sense resistance in the buck region, r sense(max,buck) . the selected r sense resistance must be smaller than both. boost region: in the boost region, the maximum output current capability is the least when v in is at its minimum and v out is at its maximum. therefore r sense must be chosen to meet the output current requirements under these conditions. start by finding the boost region duty cycle when v in is minimum and v out is maximum using: dc (max,m3,boost) ? 1? v in(min) v out(max) ? ? ? ? ? ? ? 100% for example, an application with a v in range of 12v to 48v and v out set to 36v will have: dc (max,m3,boost) ? 1? 12v 36v ? ? ? ? ? ? ? 100% = 67% http:///
LT8705 22 8705p for more information www.linear.com/8705 referring to the maximum inductor current sense volt - age graph in the typical performance characteristics section, the maximum r sense voltage at 67% duty cycle is ? 93mv, or: v rsense(max,boost, max) ? 93mv for v in = 12v, v out = 36v. next, the inductor ripple current in the boost region must be determined. if the main inductor l is not known, the maximum ripple current ? i l(max,boost) can be estimated by choosing ? i l(max,boost) to be 30% to 50% of the maximum inductor current in the boost region as follows: ? i l(max,boost) ? v out(max) ? i out(max,boost) v in(min) ? 100% %ripple ? 0.5 ? ? ? ? ? ? a where: i out(max,boost) is the maximum output load current required in the boost region %ripple is 30% to 50% for example, using v out(max) = 36v, v in(min) = 12v, i out(max,boost) = 2a and %ripple = 40% we can estimate: ? i l(max,boost) ? 36v ? 2a 12v ? 100% 40% ? 0.5 ? ? ? ? ? ? = 3a otherwise, if the inductor value is already known then ? i l(max,boost) can be more accurately calculated as follows: ? i l(max,boost) = dc (max,m3,boost) 100% ? ? ? ? ? ? ? v in(min) f ? l a where: dc (max,m3,boost) is the maximum duty cycle percent - age in the boost region as calculated previously. f is the switching frequency l is the inductance of the main inductor after the maximum ripple current is known, the maximum allowed r sense in the boost region can be calculated as follows: r sense(max,boost) = 2 ? v rsense(max,boost,max) ? v in(min) 2 ? i out(max,boost) ? v out(min) ( ) + ? i l(max,boost) ? v in(min) ( ) ? where v rsense(max,boost,max) is the maximum inductor current sense voltage as discussed in the previous section. using values from the previous examples: r sense(max,boost) = 2 ? 93mv ? 12 2 ? 2a ? 36v ( ) + 3a ? 12v ( ) = 12.4m ? buck region: in the buck region, the maximum output cur - rent capability is the least when operating at the minimum duty cycle. this is because the slope compensation ramp increases the maximum r sense voltage with increasing duty cycle. the minimum duty cycle for buck operation can be calculated using: dc (min,m2,buck) ? t on(m2,min) ? f ? 100% where t on(m2,min) is 260ns (typical value, see electrical characteristics) before calculating the maximum r sense resistance, however, the inductor ripple current must be determined. if the main inductor l is not known, the ripple current ? i l(min,buck) can be estimated by choosing ? i l(min,buck) to be 10% of the maximum inductor current in the buck region as follows: ? i l(min,buck) ? i out(max,buck) 100% 10% ? 0.5 ? ? ? ? ? ? a where: i out(max,buck) is the maximum output load current required in the buck region. applications information http:///
LT8705 23 8705p for more information www.linear.com/8705 if the inductor value is already known then ? i l(min,buck) can be calculated as follows: ? i l min,buck ( ) = dc (min,m2,buck) 100% ? ? ? ? ? ? ? v out(min) f ? l a where: dc (min,m2,buck) is the minimum duty cycle percentage in the buck region as calculated previously. f is the switching frequency l is the inductance of the main inductor after the inductor ripple current is known, the maximum allowed r sense in the buck region can be calculated as follows: r sense(max,buck) = 2 ? 86mv 2 ? i out(max,buck) ( ) ? ? i l(min,buck) final r sense value: the final r sense value should be lower than both r sense(max,boost) and r sense(max,buck) . a margin of 30% or more is recommended. figure 8 shows approximately how the maximum output current and maximum inductor current would vary with v in /v out while all other operating parameters remain constant (frequency = 350khz, inductance = 10h, r sense = 10m). this graph is normalized and accounts for changes in maximum current due to the slope compensation ramps and the effects of changing ripple current. the curve is theoretical, but can be used as a guide to predict relative changes in maximum output and inductor current over a range of v in /v out voltages. reverse current limit when the forced continuous mode is selected (mode pin low), inductor current is allowed to reverse directions and flow from the v out side to the v in side. this can lead to current sinking from the output and being forced into the input. the reverse current is at a maximum magni - tude when v c is lowest. the graph of minimum inductor current sense voltage in fcm in the typical performance characteristics section can help to determine the maximum reverse current capability. inductor selection for high efficiency, choose an inductor with low core loss, such as ferrite. also, the inductor should have low dc resistance to reduce the i 2 r losses, and must be able to handle the peak inductor current without saturating. to minimize radiated noise, use a toroid, pot core or shielded bobbin inductor. the operating frequency and inductor selection are inter - related in that higher operating frequencies allow the use of smaller inductor and capacitor values. the following sections discuss several criteria to consider when choosing an inductor value. for optimal performance, choose an inductor that meets all of the following criteria. inductor selection: adequate load current in the boost region small value inductors result in increased ripple currents and thus, due to the limited peak inductor current, decrease the maximum average current that can be provided to the load (i out ) while operating in the boost region. applications information figure 8. currents vs v in /v out ratio v in /v out (v/v) normalized current 1.0 0.8 0.6 8705 f08 0 0.4 0.2 10 0.1 1 maximum inductor current maximum output current http:///
LT8705 24 8705p for more information www.linear.com/8705 in order to provide adequate load current at low v in volt - ages in the boost region, l should be at least: l (min1,boost) ? v in(min) ? dc (max,m3,boost) 100% ? ? ? ? ? ? 2 ? f ? v rsense(max,boost,max) r sense ? i out(max) ? v out(max) v in(min) ? ? ? ? ? ? where: dc (max,m3,boost) is the maximum duty cycle per - centage of the m3 switch (see r sense selection and maximum current section). f is the switching frequency v rsense(max,boost,max) is the maximum current sense voltage in the boost region at maximum duty cycle (see r sense selection and maximum current section) negative values of l (min1,boost) indicate that the output load current i out cant be delivered in the boost region because the inductor current limit is too low. if l (min1,boost) is too large or is negative, consider reducing the r sense resistor value to increase the inductor current limit. inductor selection: subharmonic oscillations the LT8705s internal slope compensation circuits will prevent subharmonic oscillations that can otherwise oc - cur when v in /v out is less than 0.5 or greater than 2. the slope compensation circuits will prevent these oscillations provided that the inductance exceeds a minimum value (see the earlier section inductor current sensing and slope compensation for more information). choose an induc - tance greater than all of the relevant l (min) limits discussed below. negative results can be interpreted as zero. applications information in the boost region, if v out can be greater than twice v in , calculate l (min2,boost) as follows: l (min2,boost) = v out(max) ? v in(min) ? v out(max) v out(max) ? v in(min) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r sense 0.08 ? f h in the buck region, if v in can be greater than twice v out , calculate l (min1,buck) as follows: l (min1,buck) = v in(max) ? 1? v out(max) v in(max) ? v out(min) ? ? ? ? ? ? ? r sense 0.08 ? f h inductor selection: maximum current rating the inductor must have a rating greater than its peak operating current to prevent inductor saturation resulting in efficiency loss. the peak inductor current in the boost region is: i l(max,boost) ? i out(max) ? v out(max) v in(min) + v in(min) ? dc (max,m3,boost 100% ? ? ? ? ? ? 2 ? l ? f ? ? ? ? ? ? ? ? ? ? ? ? a where dc (max,m3,boost) is the maximum duty cycle percentage of the m3 switch (see r sense selection and maximum current section). http:///
LT8705 25 8705p for more information www.linear.com/8705 applications information the peak inductor current when operating in the buck region is: i l(max,buck) ? i out(max) + v out(min) ? dc (max,m2,buck 100% ? ? ? ? ? ? 2 ? l ? f ? ? ? ? ? ? ? ? ? ? ? ? a where dc (max,m2,buck) is the maximum duty cycle per - centage of the m2 switch in the buck region given by: dc max,m2,buck ( ) ? 1? v out(min) v in(max) ? ? ? ? ? ? ? 100% note that the inductor current can be higher during load transients and if the load current exceeds the expected maximum i out(max) . it can also be higher during start- up if inadequate soft-start capacitance is used or during output shorts. consider using the output current limiting to prevent the inductor current from becoming excessive. output current limiting is discussed later in the input/ output current monitoring and limiting section. care - ful board evaluation of the maximum inductor current is recommended. power mosfet selection and efficiency considerations the LT8705 requires four external n-channel power mos - fets, two for the top switches (switches m1 and m4, shown in figure 3) and two for the bottom switches (switches m2 and m3, shown in figure 3). important parameters for the power mosfets are the breakdown voltage, v br,dss , threshold voltage, v gs,th , on-resistance, r ds(on) , reverse- transfer capacitance, c rss (gate-to-drain capacitance), and maximum current, i ds(max) . the gate drive voltage is set by the 6.35v gatev cc supply. consequently, logic-level threshold mosfets must be used in LT8705 applications. it is very important to consider power dissipation when selecting power mosfets. the most efficient circuit will use mosfets that dissipate the least amount of power. power dissipation must be limited to avoid overheating that might damage the devices. for most buck-boost ap - plications the m1 and m3 switches will have the highest power dissipation where m2 will have the lowest unless the output becomes shorted. in some cases it can be helpful to use two or more mosfets in parallel to reduce power dissipation in each device. this is most helpful when power is dominated by i 2 r losses while the mosfet is on. the additional capacitance of connecting mosfets in parallel can sometimes slow down switching edge rates and consequently increase total switching power losses. the following sections provide guidelines for calculating power consumption of the individual mosfets. from a known power dissipation, the mosfet junction tempera - ture can be obtained using the following formula: t j = t a + p ? r th(ja) where: t j is the junction temperature of the mosfet t a is the ambient air temperature p is the power dissipated in the mosfet r th(ja) is the mosfets thermal resistance from the junction to the ambient air. refer to the manufacturers data sheet. r th(ja) normally includes the r th(jc) for the device plus the thermal resistance from the case to the ambient tem - perature r th(jc) . compare the calculated value of t j to the manufacturers data sheets to help choose mosfets that will not overheat. switch m1: the power dissipation in switch m1 comes from two primary components: (1) i 2 r power when the switch is fully turned on and inductor current is flowing through the drain to source connections and (2) power http:///
LT8705 26 8705p for more information www.linear.com/8705 applications information dissipated while the switch is turning on or off. as the switch turns on and off a combination of high current and high voltage causes high power dissipation in the mosfet. although the switching times are short, the aver - age power dissipation can still be significant and is often the dominant source of power in the mosfet. depending on the application, the maximum power dissipation in the m1 switch can happen in the buck region when v in is highest, v out is highest, and switching power losses are greatest or in the boost region when v in is smallest, v out is highest and m1 is always on. switch m1 power consumption can be approximated as: p m1 = p i 2 r + p switching ? v out v in ? i out ? ? ? ? ? ? 2 ? r ds(on) ? ? ? ? ? ? ? ? ? + v in ? i out ? f ? t rf1 ( ) w where: the p switching term is 0 in the boost region t rf1 is the average of the sw1 pin rise and fall times. typical values are 20ns to 40ns depending on the mosfet capacitance and v in voltage. an estimate of t rf1 can be calculated from the following equation. verify this with direct measurements. since switching power loss is proportional to t rf1 , this equation is useful to understand how capacitance and gate resistance effects power loss in various mosfets: t rf1 ? v in ? c rss ? 2 + r gate 0.8 ? ? ? ? ? ? c rss (gate-to-drain capacitance) is usually specified by the mosfet manufacturers. if c rss is not specified, but q gd is, approximate c rss as: c rss = q gd v ds where v ds is the voltage specified for the given q gd . r gate is the series gate resistance of the mosfet (usually < 1?see manufacturers data sheet) plus any additional resistance connected in series with the mosfets gate. is a normalization factor (unity at 25c) accounting for the significant variation in mosfet on-resistance with temperature, typically about 0.4%/c, as shown in figure 9. for a maximum junction temperature of 125c, using a value = 1.5 is reasonable. since the switching power (p switching ) often dominates, look for mosfets with lower c rss or consider operating at a lower frequency to minimize power loss and increase efficiency. junction temperature (c) ?50 normalized on-resistance () 1.0 1.5 150 8705 f09 0.5 0 0 50 100 2.0 figure 9. normalized mosfet r ds(on) vs temperature switch m2: in most cases the switching power dissipa - tion in the m2 switch is quite small and i 2 r power losses dominate. i 2 r power is greatest in the buck region where the switch operates as the synchronous rectifier. higher v in and lower v out causes the m2 switch to be on for the most amount of time, leading to the highest power consumption. the m2 switch power consumption in the buck region can be approximated as: p (m2,buck) ? v in ? v out v in ? i out(max) 2 ? r ds(on) ? ? ? ? ? ? ? w http:///
LT8705 27 8705p for more information www.linear.com/8705 applications information switch m3: switch m3 operates in the boost and buck- boost regions as a control switch. similar to the m1 switch, the power dissipation comes from i 2 r power and switching power. the maximum power dissipation is when v in is the lowest and v out is the highest. the following expression approximates the power dissipation in the m3 switch under those conditions: p m3 = p i 2 r + p switching ? v out ? v in ( ) ? v out v in 2 ? i out 2 ? r ds(on) ? ? ? ? ? ? ? + v out 2 ? i out ? f ? t rf2 v in ? ? ? ? ? ? w where the total power is 0 in the buck region. t rf2 is the average of the sw2 pin rise and fall times and, similar to t rf1 , is typically 20ns to 40ns or can be estimated using: t rf2 ? v out ? c rss ? 2 + r gate 0.8 ? ? ? ? ? ? as with the m1 switch, the switching power (p switching ) often dominates. look for mosfets with lower c rss or consider operating at a lower frequency to minimize power loss and increase efficiency. switch m4: in most cases the switching power dissipa - tion in the m4 switch is quite small and i 2 r power losses dominate. i 2 r power is greatest in the boost region where the switch operates as the synchronous rectifier. lower v in and higher v out increases the inductor current for a given i out , leading to the highest power consumption. the m4 switch power consumption in the boost region can be approximated as: p (m4,boost) ? v out v in ? i out 2 ? ? r ds(on) ? ? ? ? ? ? w gate resistors: in some cases it can be beneficial to add 1 to 10 of resistance between some of the nmos gate pins and their respective gate driver pins on the LT8705 (i.e., tg1, bg1, tg2, bg2). due to parasitic inductance and capacitance, ringing can occur on sw1 or sw2 when low capacitance mosfets are turned on/off too quickly. the ringing can be of greatest concern when operating the mosfets or the LT8705 near the rated voltage limits. additional gate resistance slows the switching speed, minimizing the ringing. excessive gate resistance can have two negative side effects on performance: 1. slowing the switch transition times can also increase power dissipation in the switch. this is described above in the switch m1 and switch m3 sections. 2. capacitive coupling from the sw1 or sw2 pin to the switch gate node can turn it on when its supposed to be off, thus increasing power dissipation. with too much gate resistance, this would most commonly happen to the m2 switch when sw1 is rising. careful board evaluation should be performed when optimizing the gate resistance values. sw1 and sw2 pin ringing can be affected by the inductor current levels, therefore board evaluation should include measurements at a wide range of load currents. when performing pcb measurements of the sw1 and sw2 pins, be sure to use a very short ground post from the pcb ground to the scope probe ground sleeve in order to minimize false inductive voltages readings. c in and c out selection input and output capacitance is necessary to suppress voltage ripple caused by discontinuous current moving in and out of the regulator. a parallel combination of capaci - tors is typically used to achieve high capacitance and low esr (equivalent series resistance). dry tantalum, special http:///
LT8705 28 8705p for more information www.linear.com/8705 applications information polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. capacitors with low esr and high ripple current ratings, such as os-con and poscap are also available. ceramic capacitors should be placed near the regulator input and output to suppress high frequency switching spikes. a ceramic capacitor, of at least 1f at the maximum v in operating voltage, should also be placed from v in to gnd as close to the LT8705 pins as possible. due to their excellent low esr characteristics ceramic capacitors can significantly reduce input ripple voltage and help reduce power loss in the higher esr bulk capacitors. x5r or x7r dielectrics are preferred, as these materials retain their capacitance over wide voltage and temperature ranges. many ceramic capacitors, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired operating voltage. input capacitance: discontinuous input current is highest in the buck region due to the m1 switch toggling on and off. make sure that the c in capacitor network has low enough esr and is sized to handle the maximum rms current. for buck operation, the input rms current is given by: i rms ? i out(max) ? v out v in ? v in v out ? 1 this formula has a maximum at v in = 2v out , where i rms = i out(max) /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. the maximum input ripple due to the voltage drop across the esr is approximately: ? v (buck,esr) ? v in(max) ? i out(max) v out(min) ? esr output capacitance: the output capacitance (c out ) is necessary to reduce the output voltage ripple caused by discontinuities and ripple in the output and load currents. the effects of esr and the bulk capacitance must be considered when choosing the right capacitor for a given output ripple voltage. the steady-state output ripple due to charging and discharging the bulk output capacitance is given by the following equations: ? v boost,cap ( ) ? i out ? v out ? v in ( ) c out ? v in ? f v for v out > v in ? v (buck,cap) ? v out ? 1? v out v in ? ? ? ? ? ? 8 ? l ? f 2 ? c out v for v out < v in the maximum output ripple due to the voltage drop across the esr is approximately: ? v (boost,esr) ? v out(max) ? i out(max) v in(min) ? esr as with c in , multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. schottky diode (d1, d2) selection the schottky diodes, d1 and d2, shown in figure 1, con - duct during the dead time between the conduction of the power mosfet switches. they are intended to prevent the body diodes of synchronous switches m2 and m4 from turning on and storing charge. for example, d2 significantly reduces reverse-recovery current between switch m4 turn-off and switch m3 turn-on, which improves converter efficiency, reduces switch m3 power dissipation and reduces noise in the inductor current sense resistor (r sense ) when m3 turns on. in order for the diode to be effective, the inductance between it and the synchronous switch must be as small as possible, mandating that these components be placed adjacently. for applications with high input or output voltages (typi - cally >40v) avoid schottky diodes with excessive reverse- leakage currents particularly at high temperatures. some ultralow v f diodes will trade off increased high temperature leakage current for reduced forward voltage. diode d1 http:///
LT8705 29 8705p for more information www.linear.com/8705 applications information boost diodes d b1 and d b2 : although schottky diodes have the benefit of low forward voltage drops, they can exhibit high reverse current leakage and have the potential for thermal runaway under high voltage and temperature conditions. silicon diodes are thus recommended for diodes d b1 and d b2 . make sure that d b1 and d b2 have reverse breakdown voltage ratings higher than v in(max) and v out(max) and have less than 1ma of reverse leakage current at the maximum operating junction temperature. make sure that the reverse leakage current at high op - erating temperatures and voltages wont cause thermal runaway of the diode. in some cases it is recommended that up to 5 of resis - tance is placed in series with d b1 and d b2 . the resistors reduce surge currents in the diodes and can reduce ringing at the sw and boost pins of the ic. since sw pin ringing is highly dependent on pcb layout, sw pin edge rates and the type of diodes used, careful measurements directly at the sw pins of the ic are recommended. if required, a single resistor can be placed between gatev cc and the common anodes of d b1 and d b2 (as in the front page application) or by placing separate resistors between the cathodes of each diode and the respective boost pins. excessive resistance in series with d b1 and d b2 can reduce the boost-sw capacitor voltage when the m2 or m3 on-times are very short and should be avoided. output voltage the LT8705 output voltage is set by an external feedback resistive divider carefully placed across the output capaci - tor. the resultant feedback signal (fbout) is compared with the internal precision voltage reference (typically 1.207v) by the error amplifier ea4. the output voltage is given by the equation: v out = 1.207v ? 1 + r fbout1 r fbout2 ? ? ? ? ? ? where r fbout1 and r fbout2 are shown in figure 1. can have a reverse voltage up to v in and d2 can have a reverse voltage up to v out . the combination of high reverse voltage and current can lead to self heating of the diode. besides reducing efficiency, this can increase leakage current which increases temperatures even further. choose packages with lower thermal resistance ( ja ) to minimize self heating of the diodes. topside mosfet driver supply (c b1 , d b1 , c b2 , d b2 ) the top mosfet drivers (tg1 and tg2) are driven digitally between their respective sw and boost pin voltages. the boost voltages are biased from floating bootstrap capacitors c b1 and c b2 , which are normally recharged through external silicon diodes d b1 and d b2 when the respective top mosfet is turned off. the capacitors are charged to about 6.3v (about equal to gatev cc ) forcing the v boost1-sw1 and v boost2-sw2 voltages to be about 6.3v. the boost capacitors c b1 and c b2 need to store about 100 times the gate charge required by the top switches m1 and m4. in most applications, a 0.1f to 0.47f, x5r or x7r dielectric capacitor is adequate. the bypass capacitance from gatev cc to gnd should be at least ten times the c b1 or c b2 capacitance. boost capacitor charge control block: when the LT8705 operates exclusively in the buck or boost region, one of the top mosfets, m1 or m4, can be constantly on. this prevents the respective bootstrap capacitor, c b1 or c b2 , from being recharged through the silicon diode, d b1 or d b2 . the boost capacitor charge control block (see fig - ure 1) keeps the appropriate boost pin charged in these cases. when the m1 switch is always on (boost region), current is automatically drawn from the cspout and/or boost2 pins to charge the boost1 capacitor as needed. when the m4 switch is always on (buck region) current is drawn from the csnin and/or boost1 pins to charge the boost2 capacitor. because of this function, cspin and csnin should be connected to a potential close to v in . tie both pins to v in if they are not being used. also, cspout and csnout should always be tied to a potential close to v out , or be tied directly to v out if not being used. http:///
LT8705 30 8705p for more information www.linear.com/8705 applications information ? + ? + ea2 imon_in 8705 f10 c imon_in r imon_in cspin r sense1 from dc power supply to remainder of system to boost capacitor charge control block csnin LT8705 input current v c 1.208v fault control 1.61v ? + g m = 1m a7 figure 10. input current monitor and limit figure 11. output current monitor and limit ? + ? + ea1 imon_out 8705 f11 c imon_out r imon_out cspout r sense2 from controller v out to system v out csnout LT8705 output current v c 1.208v fault control 1.61v ? + g m = 1m a8 to boost capacitor charge control block input voltage regulation or undervoltage lockout by connecting a resistor divider between v in , fbin and gnd, the fbin pin provides a means to regulate the input voltage or to create an undervoltage lockout function. referring to error amplifier ea3 in the block diagram, when fbin is lower than the 1.205v reference v c is pulled low. for example, if v in is provided by a relatively high impedance source (i.e., a solar panel) and the current draw pulls v in below a preset limit, v c will be reduced, thus reducing current draw from the input supply and limiting the voltage drop. note that using this function in forced continuous mode (mode pin low) can result in current being drawn from the output and forced into the input. if this behavior is not desired then use discontinuous or burst mode operation. to set the minimum or regulated input voltage use: v in(min) = 1.205v ? 1 + r fbin1 r fbin2 ? ? ? ? ? ? where r fbin1 and r fbin2 are shown in figure 1. make sure to select r fbin1 and r fbin2 such that fbin doesnt exceed 30v (absolute maximum rating) under maximum v in conditions. this same technique can be used to create an undervolt - age lockout if the LT8705 is not in forced continuous mode. when in burst mode operation or discontinuous mode, forcing v c low will stop all switching activity. note that this does not reset the soft-start function, therefore resumption of switching activity will not be accompanied by a soft-start. input/output current monitoring and limiting the LT8705 has independent input and output current monitor circuits that can be used to monitor and/or limit the respective currents. the current monitor circuits work as shown in figures 10 and 11. as described in the topside mosfet driver supply section, the csnin and cspout pins are also connected to the boost capacitor charge control block (also see figure?1) and can draw current in certain conditions. in addition, all four of the current sense pins can draw bias current under normal operating conditions. as such, do not place resistors in series with any of the csxin or csxout pins. also, because of their use with the boost capacitor charge control block, tie the cspin and csnin pins to v in and tie the imon_in pin to ground when the input current http:///
LT8705 31 8705p for more information www.linear.com/8705 applications information sensing is not in use. similarly, the cspout and csnout pins should be tied to v out and imon_out should be grounded when not in use. the remaining discussion refers to the input current moni - tor circuit. all discussion and equations are applicable to the output current monitor circuit, substituting pin and device names as appropriate. current monitoring: for input current monitoring, cur - rent flowing through r sense1 develops a voltage across cspin and csnin which is multiplied by 1ma/v (typical), converting it to a current that is forced out of the imon_in pin and into resistor r imon_in (note: negative cspin to csnin voltages are not multiplied and no current flows out of imon_in in that case). the resulting imon_in volt - age is then proportional to the input current according to: v imon _in = i rsense1 ? r sense1 ? 1m a v ? r imon _in ? ? ? ? ? ? for accurate current monitoring, the cspin and csnin voltages should be kept above 1.5v (cspout and csnout pins should be kept above 0v). also, the differential volt - age v cspin-csnin should be kept below 100mv due to the limited amount of current that can be driven out of imon_in. finally, the imon_in voltage must be filtered with capacitor c imon_in because the input current often has ripple and discontinuities depending on the LT8705s region of operation. c imon_in should be chosen by the equation: c imon _in > 100 f ? r imon _in ? ? ? ? ? ? f where f is the switching frequency, to achieve adequate filtering. additional capacitance, bringing the c imon_in total to 0.1f to 1f, may be necessary to maintain loop stability if the imon_in pin is used in a constant-current regulation loop. current limiting: as shown in figure 10, imon_in voltages exceeding 1.208v (typical) cause the v c voltage to reduce, thus limiting the inductor and input currents. r imon_in can be selected for a desired input current limit using: r imon _in = 1.208v i rsense(limit) ? 1m a v ? r sense1 ? ? ? ? ? ? ? ? ? ? ? for example, if r sense1 is chosen to be 12.5m and the desired input current limit is 4a then: r imon _in = 1.208v 4a ? 1m a v ? 12.5m ? = 24.2k ? review the electrical characteristics and the imon output currents graph in the typical performance characteris - tics section to understand the operational limits of the imon_out and imon_in currents. overcurrent fault: if imon_in exceeds 1.61v (typical), a fault will occur and switching activity will stop (see fault conditions earlier in the data sheet). the fault current is determined by: i rsense1(fault) = 1.61v 1.208v ? i rsense1(limit) ? ? ? ? ? ? a for example, an input current limit set to 4a would have a fault current limit of 5.3a. output overvoltage if the output voltage is higher than the value set by the fbout resistor divider, the LT8705 will respond according to the mode and region of operation. in forced continu - ous mode, the LT8705 will sink current into the input (see the reverse current limit discussion in the applications information section for more information). in discontinu - ous mode and burst mode operation, switching will stop and the output will be allowed to remain high. http:///
LT8705 32 8705p for more information www.linear.com/8705 applications information intv cc regulators and extv cc connection the LT8705 features two pnp ldos (low dropout regu - lators) that regulate the 6.35v (typical) intv cc pin from either the v in or extv cc supply pin. intv cc powers the mosfet gate drivers via the required gatev cc connec - tion and also powers the ldo33 pin regulator and much of the LT8705s internal control circuitry. the intv cc ldo selection is determined automatically by the extv cc pin voltage. when extv cc is lower than 6.22v (typical), intv cc is regulated from the v in ldo. after extv cc rises above 6.4v (typical), intv cc is regulated by the extv cc ldo instead. overcurrent protection circuitry typically limits the maximum current draw from either ldo to 127ma. when gatev cc and intv cc are below 4.65v, during start-up or during an overload condition, the typical current limit is reduced to 42ma. the intv cc pin must be bypassed to ground with a minimum 4.7f ceramic capacitor placed as close as possible to the intv cc and gnd pins. an ad - ditional ceramic capacitor should be placed as close as possible to the gatev cc and gnd pins to provide good bypassing to supply the high transient current required by the mosfet gate drivers. 1f to 4.7f is recommended. power dissipated in the intv cc ldos must be minimized to improve efficiency and prevent overheating of the LT8705. since ldo power dissipation is proportional to the input voltage and v in can be as high as 80v in some applications, the extv cc pin is available to regulate in - tv cc from a lower input voltage. the extv cc pin is con - nected to v out in many applications since v out is often regulated to a much lower voltage than the maximum v in . during start-up, power for the mosfet drivers, control circuits and the ldo33 pin is derived from v in until v out / extv cc rises above 6.4v, after which the power is derived from v out /extv cc . this works well, for example, in a case where v out is regulated to 12v and the maximum v in voltage is 40v. extv cc can be floated or grounded when not in use or can also be connected to an external power supply if available. the maximum current drawn through the intv cc ldo occurs under the following conditions: 1. large (capacitive) mosfets are being driven at high frequencies. 2. v in and/or v out is high, thus requiring more charge to turn the mosfet gates on and off. 3. the ldo33 pin output current is high. 4. in some applications, ldo current draw is maximum when the part is operating in the buck-boost region where v in is close to v out since all four mosfets are switching. to check for overheating find the operating conditions that consume the most power in the LT8705 (p LT8705 ). this will often be under the same conditions just listed that maximize ldo current. under these conditions monitor the clkout pin duty cycle to measure the approximate die temperature. see the junction temperature measurement section for more information. powering intv cc from v out /extv cc can also provide enough gate drive when v in drops as low as 2.8v. this allows the part to operate with a reduced input voltage after the output gets into regulation. the following list summarizes the three possible connec - tions for extv cc : 1. ext v cc left open (or grounded). this will cause intv cc to be powered from v in through the internal 6.35v regulator at the cost of a small efficiency penalty. 2. extv cc connected directly to v out (v out > 6.4v). this is the normal connection for the regulator and usually provides the highest efficiency. 3. extv cc connected to an external supply. if an external supply is available greater than 6.4v (typical) it may be used to power extv cc . http:///
LT8705 33 8705p for more information www.linear.com/8705 applications information loop compensation the loop stability is affected by a number of factors includ - ing the inductor value, output capacitance, load current, v in , v out and the v c resistor and capacitors. the LT8705 uses internal transconductance error amplifiers driving v c to help compensate the control loop. for most applications a 3.3nf series capacitor at v c is a good value. the parallel capacitor (from v c to gnd) is typically 1/10th the value of the series capacitor to filter high frequency noise. a larger v c series capacitor value may be necessary if the output capacitance is reduced. a good starting value for the v c series resistor is 20k. lower resistance will improve stability but will slow the loop response. use a trim pot instead of a fixed resistor for initial bench evaluation to determine the optimum value. ldo33 pin regulator the LT8705 includes a low dropout regulator (ldo) to regulate the ldo33 pin to 3.3v. this pin can be used to power external circuitry such as a microcontroller or other desired peripherals. the input supply for the ldo33 pin regulator is intv cc . therefore intv cc must have sufficient voltage, typically >4.0v, to properly regulate ldo33. the ldo33 and intv cc regulators are enabled by the shdn pin and are not affected by swen. the ldo33 pin regulator has overcurrent protection circuitry that typically limits the output current to 17.25ma. an undervoltage lockout monitoring ldo disables switching activity when ldo33 falls below 3.04v (typical). ldo33 should be bypassed locally with 0.1f or more. voltage lockouts the LT8705 contains several voltage detectors to make sure the chip is under proper operating conditions. table?1 summarizes the pins that are monitored and also indicates the state that the LT8705 will enter if an under or overvolt - age condition is detected. the conditions are listed in order of priority from top to bottom. if multiple over/undervoltage conditions are detected, the chip will enter the state listed highest on the table. due to their accurate thresholds, configurable undervolt - age lockouts (uvlos) can be implemented using the shdn , swen and in some cases, fbin pin. the uvlo function sets the turn on/off of the LT8705 at a desired minimum input voltage. for example, a resistor divider can be connected between v in , shdn and gnd as shown in figures?1 and 14. from the electrical characteristics, shdn has typical rising and falling thresholds of 1.234v and 1.184v respectively. the falling threshold for turning off switching activity can be chosen using: r shdn1 = r shdn2 ? v (in,chip _ off,falling) ? 1.184v ( ) 1.184v ? for example, choosing r shdn2 = 20k and a falling v in threshold of 5.42v results in: r shdn1 = 20k ? ? 5.42v ? 1.184v ( ) 1.184v = 71.5k ? the rising threshold for enabling switching activity would be: v (in,chip _ off,rising) = v (in,chip _ off,falling) ? 1.234v 1.184v or 5.65v in this example. table 1: voltage lockout conditions pin approximate voltage condition chip state (figure 2) read section v in <2.5v chip off operation: start-up shdn <1.18v chip off intv cc and gatev cc <4.65v switcher off swen <1.18v switcher off ldo33 <3.04 switcher off imon_in >1.61v fault operation: fault conditions imon_out >1.61v fault fbin <1.205v applications information: input voltage regulation or undervoltage lockout http:///
LT8705 34 8705p for more information www.linear.com/8705 applications information similar calculations can be used to select a resistor divider connected to swen that would stop switching activity dur - ing an undervoltage condition. make sure that the divider doesnt cause swen to exceed 7v (absolute maximum rating) under maximum v in conditions. using the fbin pin as an undervoltage lockout is discussed in the input voltage regulation or undervoltage lockout section. inductor current sense filtering certain applications may require filtering of the inductor current sense signals due to excessive switching noise that can appear across r sense . higher operating voltages, higher values of r sense , and more capacitive mosfets will all contribute additional noise across r sense when the sw pins transition. the csp/csn sense signals can be filtered by adding one of the rc networks shown in figures 12a and 12b. most pc board layouts can be drawn to accommodate either network on the same board. the network should be placed as close as possible to the ic. the network in figure 12b can reduce common mode noise seen by the csp and csn pins of the LT8705 at the expense of some increased ground trace noise as current passes through the capacitors. a short direct path from the capacitor grounds to the ic ground should be used on the pc board. resistors greater than 10 should be avoided as this can increase offset voltages at the csp/csn pins. the rc product should be kept to less than 30ns. junction temperature measurement the duty cycle of the clkout signal is linearly proportional to the die junction temperature, t j . measure the duty cycle of the clkout signal and use the following equation to approximate the junction temperature: t j ? dc clkout ? 34.4% 0.325% c where dc clkout is the clkout duty cycle in % and t j is the die junction temperature in c. the actual die tem - perature can deviate from the above equation by 10c thermal shutdown if the die junction temperature reaches approximately 165c, the part will go into thermal shutdown. the power switch will be turned off and the intv cc and ldo33 regulators will be turned off (see figure 2). the part will be re-enabled when the die temperature has dropped by ~5c (nominal). after re-enabling, the part will start in the switcher off state as shown in figure 2. the part will then initialize, perform a soft-start, then enter normal operation as long as the die temperature remains below approximately 165c. efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in LT8705 circuits: 1. switching losses. these losses arises from the brief amount of time switch m1 or switch m3 spends in the saturated region during switch node transitions. power loss depends upon the input voltage, load current, driver strength and mosfet capacitance, among other fac - tors. see the power mosfet selection and efficiency considerations section for more details. r sense 1nf csp csn LT8705 8705 f12a 10 10 figure 12. inductor current sense filter (12a) (12b) r sense 1nf 1nf csp csn LT8705 8705 f12b 10 10 http:///
LT8705 35 8705p for more information www.linear.com/8705 applications information 2. dc i 2 r losses. these arise from the resistances of the mosfets, sensing resistors, inductor and pc board traces and cause the efficiency to drop at high output currents. 3. intv cc current. this is the sum of the mosfet driver current, ldo33 pin current and control currents. the intv cc regulators input voltage times the current represents lost power. this loss can be reduced by supplying intv cc current through the extv cc pin from a high efficiency source, such as the output or alternate supply if available. also, lower capacitance mosfets can reduce intv cc current and power loss. 4. c in and c out loss. the input capacitor has the difficult job of filtering the large rms input current to the regu - lator in buck mode. the output capacitor has the more difficult job of filtering the large rms output current in boost mode. both c in and c out are required to have low esr to minimize the ac i 2 r loss and sufficient capacitance to prevent the rms current from causing additional upstream losses in fuses or batteries. 5. other losses. schottky diodes d1 and d2 are respon - sible for conduction losses during dead time and light load conduction periods. inductor core loss occurs predominately at light loads. when making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. if one makes a change and the input current decreases, then the efficiency has increased. if there is no change in input current, then there is no change in efficiency. circuit board layout checklist the basic circuit board layout requires a dedicated ground plane layer. also, for high current, a multilayer board provides heat sinking for power components. ? the ground plane layer should not have any traces and should be as close as possible to the layer with the power mosfets. gnd v out c out l r sense 8705 f13b m4 m3 m2 m1 sw1 sw2 d1 d2 v in c in LT8705 ckt figure 13. switches layout (13a) (13b) m3 m4 m1 m2 LT8705 ckt d2 d1 v out v in sw1 sw2 l r sense gnd 8705 f13a c out c in ? the high di/dt path formed by switch m1, switch m2, d1, r sense and the c in capacitor should be compact with short leads and pc trace lengths. the high di/dt path formed by switch m3, switch m4, d2 and the c out capacitor also should be compact with short leads and pc trace lengths. two layout examples are shown in figures 13a and 13b. http:///
LT8705 36 8705p for more information www.linear.com/8705 ? avoid running signal traces parallel to the traces that carry high di/dt current because they can receive in - ductively coupled voltage noise. this includes the sw1, sw2, tg1 and tg2 traces to the controller. ? use immediate vias to connect the components (includ - ing the LT8705s gnd pins) to the ground plane. use several vias for each power component. ? minimize parasitic sw pin capacitance by removing gnd and v in copper from underneath the sw1 and sw2 regions. ? except under the sw pin regions, flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power components. connect the copper areas to a dc net (e.g., quiet gnd). ? partition the power ground from the signal ground. the small-signal component grounds should not return to the ic gnd through the power ground path. ? place switch m2 and switch m3 as close to the controller as possible, keeping the gnd, bg and sw traces short. ? minimize inductance from the sources of m2 and m3 to r sense by making the trace short and wide. ? keep the high dv/dt nodes sw1, sw2, boost1, boost2, tg1 and tg2 away from sensitive small-signal nodes. ? the output capacitor (C) terminals should be connected as closely as possible to the (C) terminals of the input capacitor. ? connect the top driver boost capacitor, c b1 , closely to the boost1 and sw1 pins. connect the top driver boost capacitor, c b2 , closely to the boost2 and sw2 pins. ? connect the input capacitors, c in , and output capacitors, c out , closely to the power mosfets. these capacitors carry the mosfet ac current in the boost and buck regions. ? connect the fbout and fbin pin resistor dividers to the (+) terminals of c out and c in respectively. small fbout/fbin bypass capacitors may be connected closely to the LT8705s gnd pin if needed. the resistor connections should not be along the high current or noise paths. ? route current sense traces (csp/csn, cspin/csnin, cspout/csnout) together with minimum pc trace spacing. avoid having sense lines pass through noisy areas, such as switch nodes. the optional filter network capacitor between csp and csn should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the r sense resistors. ? connect the v c pin compensation network closely to the ic, between v c and the signal ground pins. the capacitor helps to filter the effects of pcb noise and output voltage ripple voltage from the compensation loop. ? connect the intv cc and gatev cc bypass capacitors close to the ic. the capacitors carry the mosfet driv - ers current peaks. design example v in = 8v to 25v v out = 12v i out(max) = 5a f = 350khz maximum ambient temperature = 60c applications information http:///
LT8705 37 8705p for more information www.linear.com/8705 applications information r t selection: choose the r t resistor for the free-running oscillator frequency using: r t = 43,750 f osc ? 1 ? ? ? ? ? ? k ? = 43,750 350 ? 1 ? ? ? ? ? ? = 124k ? r sense selection: start by calculating the maximum duty cycle in the boost region: dc (max,m3,boost) ? 1? v in(min) v out(max) ? ? ? ? ? ? ? 100% = 1? 8v 12v ? ? ? ? ? ? ? 100% = 33% next, from the maximum inductor current sense voltage vs duty cycle graph in the typical performance charac - teristics section: v rsense(max,boost,max) ? 107mv next, estimate the maximum and minimum inductor cur - rent ripple in the boost and buck regions respectively: ? i l(max,boost) ? v out(max) ? i out(max,boost) v in(min) ? 100% %ripple ? 0.5 ? ? ? ? ? ? a = 12v ? 5a 8v ? 100% 40% ? 0.5 ? ? ? ? ? ? = 3.75a ? i l(min,buck) ? i out(max,buck) 100% 10% ? 0.5 ? ? ? ? ? ? a = 5a 100% 10% ? 0.5 ? ? ? ? ? ? = 0.53a now calculate the maximum r sense values in the boost and buck regions to be: r sense(max,boost) = 2 ? v rsense(max,boost,max) ? v in(min) 2 ? i out(max,boost) ? v out(min) ( ) + ? i l(max,boost) ? v in(min) ( ) ? = 2 ? 107mv ? 8v 2 ? 5a ? 12v ( ) + 3.75a ? 8v ( ) = 11.4m ? r sense(max,buck) = 2 ? 86mv 2 ? i out(max,buck) ( ) ? ? i l(min,buck) ? = 2 ? 86mv 2 ? 5a ( ) ? 0.53a = 18.2m ? adding an additional 30% margin, choose r sense to be 11.4m/1.3 = 8.7m. inductor selection: with r sense known, we can now determine the minimum inductor value that will provide adequate load current in the boost region using: l (min1,boost) ? v in(min) ? dc (max,m3,boost) 100% 2 ? f ? v rsense(max,boost,max) r sense ? i out(max) ? v out(max) v in(min) ? ? ? ? ? ? h = 8v ? 33% 100% ? ? ? ? ? ? 2 ? 350khz ? 107mv 8.7mv ? 5a ? 12v 8v ? ? ? ? ? ? = 0.8h http:///
LT8705 38 8705p for more information www.linear.com/8705 to avoid subharmonic oscillations in the inductor current, choose the minimum inductance according to: l (min2,boost) = v out(max) ? v in(min) ? v out(max) v out(max) ? v in(min) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? r sense 0.08 ? f h = 12v ? 8v ? 12v 12v ? 8v ? ? ? ? ? ? ? ? ? ? ? ? ? 8.7m ? 0.08 ? 350khz = ?3.7h l (min1,buck) = v in(max) ? 1? v out(max) v in(max) ? v out(min) ? ? ? ? ? ? ? r sense 0.12 ? f = 25v ? 1? 12v 25v ? 12v ? ? ? ? ? ? ? 8.7m ? 0.08 ? 350khz = 0.6h the inductance must be higher than all of the minimum values calculated above. we will choose a 10h standard value inductor for improved margin. mosfet selection: the mosfets are selected based on voltage rating, c rss and r ds(on) value. it is important to ensure that the part is specified for operation with the available gate voltage amplitude. in this case, the amplitude is 6.35v and mosfets with an r ds(on) value specified at v gs = 4.5v can be used. select m1 and m2: with 25v maximum input voltage, mosfets with a rating of at least 30v are used. as we do not yet know the actual thermal resistance (circuit board design and airflow have a major impact) we assume that the mosfet thermal resistance from junction to ambient is 50c/w. if we design for a maximum junction temperature, t j(max) = 125c, the maximum allowable power dissipation can be calculated. first, calculate the maximum power dissipation: p d(max) = t j(max) ? t a(max) r th(ja) p d(max) = 125 c ? 60 c 50 c/w = 1.3w since maximum i 2 r power dissipation in the boost region happens when v in is minimum, we can determine the maximum allowable r ds(on) for the boost region using: p m1 = p i 2 r ? v out v in ? i out ? ? ? ? ? ? 2 ? r ds(on) ? ? ? ? ? ? ? ? ? w 1.3w ? 12v 8v ? 5a ? ? ? ? ? ? 2 ? r ds(on) ? 1.5 ? ? ? ? ? ? w and therefore r ds(on) < 15.4m ? the fairchild fdms7672 meets the specifications with a maximum r ds(on) of ~6.9m at v gs = 4.5v (~10m at 125c). checking the power dissipation in the buck region with v in maximum and v out minimum yields: p m1 = p i 2 r + p switching ? v out v in ? i out ? ? ? ? ? ? 2 ? r ds(on) ? ? ? ? ? ? ? ? ? + v in ? i out ? f ? t rf1 ( ) w p m1 ? 12v 25v ? 5a ? ? ? ? ? ? 2 ? 6.9m ? ? 1.5 ? ? ? ? ? ? + 25v ? 5a ? 350k ? 20ns ( ) = 0.06w + 0.88w = 0.94w the maximum switching power of 0.88w can be reduced by choosing a slower switching frequency. since this calculation is approximate, measure the actual rise and fall times on the pcb to obtain a better power estimate. the maximum dissipation in m2 occurs at maximum input voltage when the circuit is operating in the buck region. using the 6.9m fairchild fdms7672 the dissipation is: p (m2,buck) ? v in ? v out v in ? i out(max) 2 ? r ds(on) ? ? ? ? ? ? ? w p (m2,buck) ? 25v ? 12v 25v ? 5a ( ) 2 ? 6.9m ? ? 1.5 ? ? ? ? ? ? = 0.13w applications information http:///
LT8705 39 8705p for more information www.linear.com/8705 applications information select m3 and m4: with 12v output voltage we need mosfets with 20v or higher rating. the highest dissipation occurs in the boost region when input voltage is minimum and output current is highest. for switch m3 the dissipation is: p m3 = p i 2 r + p switching ? v out ? v in ( ) ? v out v in 2 ? i out 2 ? r ds(on) ? ? ? ? ? ? ? + v out 2 ? i out ? f ? t rf2 v in ? ? ? ? ? ? w as described in the power mosfet selection and efficiency considerations section. the maximum dissipation in switch m4 is: p m4,boost ( ) ? v out(max) v in(min) ? i out 2 ? ? r ds(on) ? ? ? ? ? ? w the fairchild fdms7672 can also be used for m3 and m4. assuming 20ns rise and fall times, the calculated power loss at the minimum 8v input voltage is then 0.82w for m3 and 0.39w for m4 output voltage: output voltage is 12v. select r fbout2 as 20k. r fbout1 is: r fbout1 = v out ? r fbout2 1.207v select r fbout1 as 200k. both r fbout1 and r fbout2 should have a tolerance of no more than 1%. capacitors: a low esr (5m) capacitor network for c in is selected. in this mode, the maximum ripple is: ? v (buck,esr) ? v in(max) ? i out(max) v out(min) ? esr ? v (buck,esr) ? 25v ? 5a 12v ? 5m ? = 52mv assuming esr dominates the ripple. having 5m of esr for the c out network sets the maxi - mum output voltage ripple at: ? v (boost,esr) ? v out(max) ? i out(max) v in(min) ? esr ? v (boost,esr) ? 12v ? 5a 8v ? 5m ? = 37.5mv assuming esr dominates the ripple. http:///
LT8705 40 8705p for more information www.linear.com/8705 figure 14. telecom voltage stabilizer typical applications 8705 f14a cspout csnout extv cc fbout intv cc gatev cc srvo_fbin srvo_fbout srvo_iin srvo_iout imon_in imon_out sync clkout v c 56.2k 202khz csnin tg1 boost1 l1 22h m4 m1 2 c in2 4.7f 4 sw1 bg1 csp csn LT8705 gnd bg2 sw2 boost2 v out 48v 5a v in 36v to 80v tg2 cspin v in shdn swen ldo33 mode fbin rt ss 3.3nf 220pf c in1 , c out2 : 220f, 100v c in2 , c out1 : 4.7f, 100v, tdk c453x7s2a475m d b1 , d b2 : central semi cmmr1u-02-lte l1: 22h, wrth 74435572200 or coilcraft ser2918h-223 m1, m3: fairchild fdms86104 m2, m4: fairchild fdms86101 *2 from tg1 to each seperate m1 gate **2 from bg2 to each seperate m3 gate 215k 71.5k 100k 20k 1f 4.7f 4.7f 10k 392k c in1 220f 2 c out1 4.7f 6 4 d b1 d b2 4.7f to boost1 4.7f + c out2 220f 2 + to boost2 0.22f 0.22f to diode d b1 to diode d b2 m2 m3 2 1nf 1nf 2* 2** 9m 10 10 load current (ma) 10 0 efficiency (%) 20 30 40 50 60 70 100 1000 8705 f14b 80 90 100 10 10000 coilcraft ser2918h-223 wurth 74435572200 v in = 36v v out = 48v ccm load current (ma) 10 0 efficiency (%) 20 30 40 50 60 70 100 1000 8705 f14c 80 90 100 10 10000 coilcraft ser2918h-223 wurth 74435572200 v in = 72v v out = 48v ccm efficiency vs output current (boost region) efficiency vs output current (buck region) note: see the front page and the typical performance characteristics section for more curves from this application circuit using the coilcraft inductor. the smaller wrth inductor is also suitable in place of the coilcraft inductor with some loss in efficiency. http:///
LT8705 41 8705p for more information www.linear.com/8705 applications information supercapacitor backup supply 8705 ta02a cspout csnout extv cc fbout intv cc gatev cc srvo_fbin srvo_fbout srvo_iin srvo_iout imon_in imon_out 47.5k sync clkout v c 14.3k 350khz csnin tg1 boost1 0.22f 0.22f to diode d b1 l1 2.2h to loads to diode d b2 m2 m1 25m m4 m3 sw1 bg1 csp csn LT8705 gnd bg2 sw2 boost2 v out 15v v in 12v tg2 cspin v in shdn swen ldo33 mode fbin rt ss 15nf c in1 , c out2 : 100f, 20v sanyo os-con 205a100m c in2 , c out1 : 22f, 25v, tdk c4532x741e226m c sc : 60f, 2.5v cooper bussman hb1840-2r5606-r d in : appropriate 2a schottky diode or ideal diode such as ltc4358, ltc4412, ltc4352, etc. d b1 , d b2 : central semi cmmr1u-02-lte l1: 2.2h, vishay ihlp-5050ce-01-2r2-m-01 m1-m4: fairchild fdms7698 220pf 124k 71.5k 20k 1k 1f 1f 15v 4.7f 10k 115k c in1 2 d in c in2 3 c out1 3 c sc 6 1.2k 6 c out2 2 4 d b1 d b2 4.7f to boost1 100k 4.7f 113k 2 2 3m 20k + + to boost2 100nf 100nf 25m 2n3904 24k d in 12v input 25m power flow 12v loads input current in excess of 2a will draw from super caps 25m limit capacitor charging current to 1a 113k 20k 115k regulate capacitors to 15v 1.2k c sc c sc c sc c sc c sc c sc 10k 1.2k 1.2k 1.2k 1.2k 1.2k 8705 ta02b d in 0v input 25m power flow loads 25m 113k 20k 115k 1.2k regulate loads to 8v c sc c sc c sc c sc c sc c sc 10k 1.2k 1.2k 1.2k 1.2k 1.2k 8705 ta02c v out 5v/div v in 5v/div i l 5a/div 20sec/div 8705 ta02d v out 5v/div v in 5v/div i l 5a/div 3sec/div 15v 8705 ta02e 8v charging v out to 15v with 1a current remove v in . loads (4a draw) regulated to 8v from supercaps http:///
LT8705 42 8705p for more information www.linear.com/8705 package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 5.00 0.10 note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 37 1 2 38 bottom view?exposed pad 5.50 ref 5.15 0.10 7.00 0.10 0.75 0.05 r = 0.125 typ r = 0.10 typ 0.25 0.05 (uh) qfn ref c 1107 0.50 bsc 0.200 ref 0.00 ? 0.05 recommended solder pad layout apply solder mask to areas that are not soldered 3.00 ref 3.15 0.10 0.40 0.10 0.70 0.05 0.50 bsc 5.5 ref 3.00 ref 3.15 0.05 4.10 0.05 5.50 0.05 5.15 0.05 6.10 0.05 7.50 0.05 0.25 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 45 chamfer uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701 rev c) http:///
LT8705 43 8705p for more information www.linear.com/8705 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 4.75 (.187) ref fe38 (ab) tssop rev b 0910 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 19 pin numbers 23, 25, 27, 29, 31, 33 and 35 are removed 20 ref 9.60 ? 9.80* (.378 ? .386) 38 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.50 (.0196) bsc 0.17 ? 0.27 (.0067 ? .0106) typ recommended solder pad layout 0.315 0.05 0.50 bsc 4.50 ref 6.60 0.10 1.05 0.10 4.75 ref 2.74 ref 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package package variation: fe38 (31) 38-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1665 rev b) exposed pad variation ab http:///
LT8705 44 8705p for more information www.linear.com/8705 ? linear technology corporation 2013 lt 0113 ? printed in usa related parts typical application part number description comments lt3791-1 60v high efficiency (up to 98%) synchronous 4-switch buck-boost dc/dc controller 4.7v v in 60v, 1.2v 60v, regulates v out , i out or i in , tssop-38 ltc3789 high efficiency (up to 98%) synchronous 4-switch buck-boost dc/dc controller 4v v in 38v, 0.8v v out 38v, ssop-28, 4mm 5mm qfn-28 lt3758 high input voltage, boost, flyback, sepic and inverting controller 5.5v v in 100v, positive or negative v out , 3mm 3mm dfn-10 or msop-10e ltc3115-1 40v, 2a synchronous buck-boost dc/dc converter 2.7v v in 40v, 2.7v v out 40v, 4mm 5mm dfn-16, tssop-20 ltm4609 high efficiency buck-boost dc/dc module regulator 4.5v v in 36v, 0.8v v out 34v, 15mm 15mm 2.8mm 12v output converter accepts 4v to 80v input (5.5v minimum to start) 8705 ta03a cspout csnout extv cc fbout intv cc gatev cc srvo_fbin srvo_fbout srvo_iin srvo_iout imon_in imon_out sync clkout 202khz v c 16.5k csnin tg1 boost1 0.22f 0.22f to diode d b1 to diode d b2 m1 2 m4 7m sw1 bg1 csp csn LT8705 gnd bg2 sw2 boost2 v out 12v 5.0a (v in 5.5v) 4.5a (v in 5.0v) 4.0a (v in 4.5v) 3.5a (v in 4.0v) v in 4v to 80v (increased v out ripple for v in > 60v) tg2 cspin v in shdn swen ldo33 mode fbin rt ss 10nf 220pf 215k 38.3k 20k 1f 4.7f 4.7f 11.3k c in1 : 220f, 100v c in2 : 4.7f, 100v, tdk c4532x7s2a475m c out1a , c out1b : 22f, 25v, tdk c4532x7r1e226m c out2 : 100f, 16v, sanyo os-con 16sa100m c out3 : 470f, 16v d b1 , d b2 : central semi cmmr1u-02-lte l1: 15h, wurth 7443631500 m1, m2: fairchild fdms86101 m3, m4: fairchild fdms7692 *2 from tg1 to each separate m1 gate 102k c in1 c in2 6 c out1a 2 4 d b1 d b2 4.7f 4.7f 22nf to boost1 100k 4.7f 2* + c out1b 3 c out2 3 + c out3 2 + to boost2 26.1k m2 15h m3 2 1nf 1nf 4m 10 10 load current (a) 0 efficiency (%) 90 95 4 8705 ta03c 85 80 1 2 3 5 100 v in = 60v v in = 40v v in = 20v v in = 12v v in = 5v v out 200mv/div v in 20v/div 10ms/div i load = 2a 8705 ta03c efficiency vs output current input transient (4v to 80v) linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/8705 http:///

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